Patents Assigned to Dongbu Electronics Co., Ltd.
  • Patent number: 7781865
    Abstract: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: August 24, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bong Jun Kim
  • Patent number: 7776671
    Abstract: The inductor for a semiconductor device comprises a first interlayer dielectric formed on a top of a silicon substrate, at least one first metal wire formed on a top of the first interlayer dielectric, a second interlayer dielectric formed on a top of the first interlayer dielectric to cover the first metal wire, at least one second metal wire formed on a top of the second interlayer dielectric and connected to the first metal wire, and an upper protective film formed on the top of the second interlayer dielectric to cover the second metal wire, wherein the first and second metal wires are alternately arranged and are formed in a spiral structure.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 17, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7772623
    Abstract: A CMOS image sensor and fabricating method can reduce leakage current of a photodiode reduced by configuring a triangular shape of a photodiode area to minimize an interface contacting the STI or performing deuterium annealing to remove dangling bonds from an interface contacting with oxide. The CMOS image sensor includes a semiconductor substrate, a device isolation layer on the semiconductor substrate, and a plurality of diodes, each having a shape minimizing an area of a boundary contacting with the device isolation layer.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 10, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Woo Seok Hyun
  • Patent number: 7772666
    Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor may be capable of improved thickness uniformity form microlenses formed at a reduced distance from the photodiodes. The CMOS image sensor can include: a semiconductor substrate on which a pixel array is formed, the pixel array including photodiodes formed on the semiconductor substrate to different depths for sensing red, green, and blue signals, respectively; an interlayer dielectric formed on the semiconductor substrate and having a trench at an upper portion of the pixel array; an insulating layer sidewall formed at a side of the trench; and a plurality of microlenses formed on the interlayer dielectric in the trench at predetermined intervals.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 10, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heui Gyun Ahn
  • Patent number: 7767536
    Abstract: A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on the gate oxide layer; a spacer provided to a sidewall of the gate; and a well region provided within the active area. The well region includes a threshold voltage adjustment doped region, a halo region, a source region, a drain region, an additional doped region, and a channel stop region, the additional doped region provided between the well region and each of the source and drain regions.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 3, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Tae Woo Kim
  • Patent number: 7767580
    Abstract: A method for fabricating a semiconductor device, including forming a gate insulating layer and a gate electrode on a substrate; forming insulating layer sidewalls at sides of the gate electrode; forming source/drain regions in surface portions of the substrate that are located, respectively, at sides of the gate electrode; forming a conductive silicide layer on the entire surface of the substrate; and selectively removing the silicide layer from areas other than the gate electrode and the source/drain regions of the substrate. The conductive silicide layer may be made by forming a silicon layer on an entire surface of the substrate; forming a conductive layer on the silicon layer; and thermal-processing the substrate such that the conductive layer reacts with the silicon layer.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: August 3, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Han Choon Lee
  • Patent number: 7767481
    Abstract: Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor substrate, a color filter layer on the dielectric layer, a planarization layer on an entire surface of the semiconductor substrate including the color filter layer, and a plurality of micro-lenses formed on the planarization layer to correspond to the color filter layer.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 3, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Sang Chul Kim, Jae Won Han
  • Patent number: 7763537
    Abstract: Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 27, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Kyu Chun
  • Patent number: 7763919
    Abstract: A CMOS image sensor capable of improving characteristics of the image sensor by preventing damage to a photodiode region and a method for manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate on which a device isolation region and an active region are defined; a photodiode region formed at the active region; a conductive plug formed on the photodiode region for connecting the photodiode region to a metal wiring; and a transistor formed enclosing the conductive plug.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 27, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Hun Han
  • Patent number: 7763533
    Abstract: Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 27, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyun Su Shin
  • Patent number: 7759214
    Abstract: Provided is a semiconductor device and method of making, incorporating a trench having rounded edges. According to an embodiment, a pad oxide layer, nitride layer, and TEOS layer are sequentially formed on a substrate. The TEOS layer, nitride layer, and pad oxide layer are dry-etched using a photosensitive layer pattern as a mask. After removing the photosensitive layer pattern, a trench is formed by dry-etching the substrate using the etched TEOS layer, nitride layer, and pad oxide layer as a mask. A portion of the pad oxide layer is pullback-etched, resulting in a first rounding of the trench. A portion of the etched nitride layer is pullback-etched and a portion of the etched TEOS layer is pullback-etched. The upper corner of the trench of the substrate is dry-etched using the pullback-etched TEOS layer, nitride layer, and pad oxide layer as a mask, resulting in a second rounding of the trench.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: July 20, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Suh Byoung Yoon
  • Patent number: 7745300
    Abstract: Disclosed is a capacitor and method for forming a capacitor in a semiconductor. The method includes the steps of: (a) forming a lower electrode pattern on a silicon semiconductor substrate; (b) etching a portion of the lower electrode pattern to a predetermined depth to form a step in the lower electrode pattern; (c) forming a dielectric layer and a upper electrode layer on an entire surface of the substrate including the lower electrode pattern; and (e) patterning the upper electrode layer and the dielectric layer to form a upper electrode pattern and a dielectric pattern.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: June 29, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Kwon Kim
  • Patent number: 7745348
    Abstract: A method of manufacturing a semiconductor device employs a PEALD method including using an organometallic Ta precursor to form a TaN thin film. As a result, a conformal TaN diffusion barrier may be formed at a temperature of 250° C. or higher, so that impurities are reduced and density is increased in the TaN thin film.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 29, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Han-Choon Lee
  • Patent number: 7745862
    Abstract: A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of transistors for electrically connecting the plurality of transistors, and a plurality of photodiodes electrically connected with the plurality of transistors and formed over the metal line.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: June 29, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyun Joon Sohn
  • Patent number: 7745266
    Abstract: The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: June 29, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Se-Yeul Bae
  • Patent number: 7745299
    Abstract: In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: June 29, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyung Sun Yun
  • Patent number: 7741667
    Abstract: Provided are a CMOS image sensor and a fabricating method thereof. The CMOS image sensor includes a device isolation layer, a plurality of photodiode regions, an interlayer insulating layer, a refracting layer, a planarizing layer, a color filter layer, and a plurality of microlenses. The refracting layer, with a higher refractive index than that of the interlayer insulating layer, is formed through the interlayer insulating layer on portions of the device isolation layer, to divide the interlayer insulating layer and give the divided portions thereof the characteristics of a waveguide.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: June 22, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sun Wook Jung
  • Patent number: 7737477
    Abstract: A CMOS image sensor and a method for manufacturing the same improve light-receiving efficiency and maintain a margin in the design of a metal line. The CMOS image sensor includes a transparent substrate including an active area having a photodiode region and a transistor region and a field area for isolation of the active area, a p-type semiconductor layer on the transparent substrate, a photodiode in the p-type semiconductor layer corresponding to the photodiode region, and a plurality of transistors in the p-type semiconductor layer corresponding to the transistor region.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: June 15, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyeon Woo Ha
  • Patent number: 7732838
    Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: June 8, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Bum Lee
  • Patent number: 7732871
    Abstract: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: June 8, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hyuk Park