Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor enlarges an area of a real image and prevents interference between adjacent pixels by forming a plurality of microlenses on a convex surface and forming a light blocking layer in the space between each of color filters. The CMOS image sensor can include photodiodes, a first planarization layer, R, G, B color filter layers, a second planarization layer having holes filled with a light blocking layer, and a plurality of microlenses.

Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) image sensor is provided. The method can include the steps of: providing a semiconductor substrate having an active region and an isolation region defined thereon; forming a photodiode at a photodiode area of the active region; forming first and second gate polys on a transistor region of the active region; forming a floating diffusion region on the semiconductor substrate between the first and second gate polys for receiving electrons transferred from the photodiode; and forming a floating diffusion node region at a part of the floating diffusion region for forming a metal contact. The floating diffusion region can be formed independently of the floating diffusion node region, so that a junction leakage current generated from the floating diffusion node region can be controlled.

Abstract: There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.

Abstract: A method is provided for measuring interface trap density in a semiconductor device. In the method, measurement parameters are input to a host computer. A pulse condition is set at a pulse generator using the measurement parameters. A pulse of a predetermined frequency generated by the pulse generator is applied to a gate of a transistor, and a charge pumping current is measured from a bulk of the transistor. A charge pumping current measurement may be repeated for a plurality of frequencies while changing the frequency until a set frequency is reached. A pure charge pumping current is calculated for each frequency where a gate tunneling leakage current is removed from the charge pumping current measured for each frequency. Interface trap density is calculated from the calculated pure charge pumping current for each frequency.

Abstract: Disclosed herein are a CMOS image sensor and a method of manufacturing the same, which can reduce current leakage through a plug connecting a photodiode and a transfer transistor to each other, and thereby provide low dark current levels. The CMOS image sensor includes a first epitaxial layer on or in a substrate. A photodiode PD is in the first epitaxial layer. A second epitaxial layer is on or in the substrate (e.g., on the first epitaxial layer). A shallow trench isolation region is in an area of the substrate. A plug is in the substrate (e.g., the second epitaxial layer) connected with the photodiode and spaced apart from the shallow trench isolation region. A transfer transistor having a gate electrode and source/drain regions is connected with the plug.

Abstract: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.

Abstract: A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile memory device includes a semiconductor substrate; a tunneling oxide layer formed on a predetermined portion of the semiconductor substrate; a floating gate formed on the tunneling oxide layer, the floating gate having a trench structure; a control gate formed inside the trench structure of the floating gate; and a gate insulating layer disposed between the floating gate and the control gate.

Abstract: Disclosed is an I/O cell for providing an output pad with an output signal, including a first drive circuit for providing the output pad with an output signal having a drive strength which is equal to a drive strength required by a basic PMOS transistor or a basic NMOS transistor, the first drive circuit further operating as an ESD protection circuit to protect the output pad from any errant electrostatic signal input thereto; and a at least one second drive circuit connected between an output of the first drive circuit and the output pad, the second drive circuit operating as an ESD protection circuit to further protect the output pad from any errant electrostatic signal input thereto.

Abstract: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

Abstract: Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is formed under the first gate oxide layer of the input/output region and on the semiconductor substrate of the core region. Nitrogen annealing is performed to form a nitrogen-rich oxide layer under the second gate oxide layer. An additional thermal process is performed to diffuse nitrogen segregated on an interface between the first gate oxide layer and the second gate oxide layer of the input/output region to a surface of the semiconductor substrate. Impurities generated during the additional thermal process are discharged to the outside.

Abstract: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.

Abstract: A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer and the metal layer are silicided due to a thermal budget applied thereto, thereby forming a metal silicide layer, and patterning the metal silicide layer based on the hard mask to form a gate.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: A printed circuit board including an opening for receiving a semiconductor package having a plurality of external connections which protrude externally from side surfaces of the semiconductor package. The board also includes a plurality of board connectors electrically interconnected to the plurality of external connections of the package and formed on sidewall of the opening, wiring patterns for electrically interconnect electronic components mounted on the printed circuit board and being electrically interconnected to the plurality of board connectors, a plurality of holes penetrating the printed circuit board, and a fastener inserted into the plurality of holes and for fastening the semiconductor package received in the opening.

Abstract: A CMOS image sensor and a method for manufacturing the same are provided, in which a nitride layer for passivation is used as a microlens to reduce topology. The CMOS image sensor includes an upper metal layer partially deposited on a dielectric layer; a first nitride layer deposited on the upper metal layer; an undoped silicon glass layer deposited on the first nitride layer and polished by chemical-mechanical polishing; color filter array elements deposited and exposed on the undoped silicon glass layer and polished by the chemical-mechanical polishing; and a second nitride layer deposited on the first nitride layer and the color filter array elements and transfer-etched after forming a sacrificial microlens on the second nitride layer.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A CMOS image sensor is provided. The CMOS image sensor can include: a plurality of photodiodes formed on a semiconductor substrate; an interlayer dielectric layer formed on an entire surface of the semiconductor substrate having the plurality of photodiodes; color filter layers including multi-layered blue color filter layers formed on the interlayer dielectric layer corresponding to respective photodiodes of the plurality of photodiodes; a planarization layer formed on the semiconductor substrate having the color filter layers; and microlenses formed on the planarization layer.

Abstract: An image sensor includes the steps of forming a sublayer including a photodiode, a transistor and a metal line on a substrate, forming a pattern layer on the sublayer to be overlapped with the photodiode and to having a curved surface, and forming a combined color filter and microlens on the pattern layer to have a curved surface.

Abstract: A method for forming shallow trench isolation in a semiconductor device including forming a pad oxide, a pad nitride, and a pore-generating layer on an entire surface of a semiconductor substrate in successive order; etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a trench in the substrate; forming a trench oxide over the entire surface of the substrate by a CVD process to fill the trench; and removing the trench oxide in an active device area while retaining the trench oxide in the trench.