Abstract: A CMOS image sensor that includes a semiconductor substrate with a plurality of photodiodes arranged at fixed intervals on the semiconductor substrate. A light-shielding layer partially overlaping the plurality of photodiodes and an insulating interlayer are formed on an entire surface of the semiconductor substrate including the plurality of photodiodes. A color filter layer having a plurality of color filters separated by a predetermined gap is formed on the insulating interlayer and a planarization layer is formed over the entire surface of the semiconductor substrate including the color filter layer. A plurality of microlenses are formed on the planarization layer in correspondence with the color filters of the color filter layer, wherein an additional structural layer, disposed between the color filter layer and the insulating interlayer, is provided to close a predetermined gap between the color filters of the color filter layer.

Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.

Abstract: A semiconductor device and a method manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing a first heat treatment process; sequentially forming a first insulating layer and a second insulating layer on the semiconductor substrate, where the etching selectivity of the first insulating layer is different from the etching selectivity of the second insulating layer; selectively etching the second insulating layer to form spacers on sidewalls of the gate electrode; selectively removing the first insulating layer to expose a source/drain area and forming a high-density N-type diffusion area in the exposed source/drain area; performing a second heat treatment process; and forming a metal silicide layer the high-density N-type diffusion area.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.

Abstract: There is provided a high voltage semiconductor device comprising: a semiconductor substrate of a first conductivity type, including a first region, a second region relatively lower than the first region, and a sloped region between the first region and the second region; a drift region of a second conductivity type, formed on the second region; a source region of the second conductivity type, disposed on the first region, and spaced apart from the drift region by the sloped region; a drain region of the second conductivity type, disposed on the drift region; a field plate positioned on the drift region in the second region; a gate insulating layer disposed between the source region and the drift region; and a gate electrode layer, which is disposed on the gate insulating layer and extends to above the field plate.

Abstract: A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor substrate; forming a seed layer on the contact hole through electroless plating process; and forming a metal interconnection in the contact hole on the seed layer.

Abstract: Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an insulating layer on the underlying conductive layer; a lower metal layer contacting inner surfaces of the contact and/or via hole and a top surface of the insulating layer; a filling layer contacting the lower barrier metal layer and at least partially filling the contact and/or via hole; an antifuse material layer contacting a top surface of the filling layer and a part of the lower metal layer; and an upper metal layer on the antifuse material layer.

Abstract: A lateral DMOS transistor having a uniform distribution of channel impurity concentration includes a drift region of a first conductivity; a body of a second conductivity, the body being disposed in the drift region and has a channel thereon; and a source region of the first conductivity, the source region being disposed within the body and having an upper region surrounded by a first impurity region of the first conductivity.

Abstract: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.

Abstract: Disclosed is a method for forming a via-hole for interconnection of metallization and/or metal wires in a semiconductor device. The present method may include the steps of: (a) forming an insulating layer on a semiconductor substrate including a lower metallization and/or metal wiring; (b) forming a mask (e.g., a photo-resist pattern) on the insulating layer; (c) dry etching the insulating layer using the photo-resist pattern as a mask to form a via-hole in the insulating layer; and (d) in the same dry etching chamber, etching a top portion of the insulating layer in the vicinity of the via-hole with an etchant comprising oxygen and argon.

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H2 in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H2 in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO2:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N2 annealing or Ar annealing.

Abstract: A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming, using an oxidation rate differential, an uneven structure in correspondence with a grain boundary of the metal layer; forming a dielectric layer on the lower electrode having the uneven structure; and forming an upper electrode on the dielectric layer.

Abstract: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer; forming a second oxide layer pattern by wet etching the second oxide layer by using the first photoresist layer pattern as a mask; forming a nitride layer pattern by dry etching the nitride layer using the second oxide layer pattern as a mask; and forming a first oxide layer pattern by etching the first oxide layer using the nitride layer pattern as a mask.

Abstract: A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench and the first electrode layer; a junction area formed on the active area; a second gate oxide layer formed on the entire surface of the substrate including the first electrode layer, the first gate oxide layer, the trench and the junction area; a tunnel oxide layer formed on a part of the second gate oxide layer corresponding to the active area; and a second electrode layer formed on the active area and in the trench.

Abstract: Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.

Abstract: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper side of the insulating layer. The second polishing step is performed, after completing the first polishing step, for planarizing the insulating interlayer.

Abstract: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area.

Abstract: A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of a second conductive type formed on the transistor region.