Abstract: A computer-implemented method for automatic generation of at least one block representing a driver function for a block-based modeling environment, wherein the driver function serves to control a hardware element of a target hardware unit, the method including preparing a description of the driver function in a formal language, reading in and evaluating the formal-language description of the driver function, and generating the block representing the driver function for modeling of the driver function in a block diagram of the modeling environment.

Abstract: A computer-based system and method for assigning at least one signal of a symbol-based program to at least one I/O functionality of a target hardware unit is provided. A modeling tool has a symbol-based program with the signal that is to be assigned. The signal to be assigned of the symbol-based program and the at least one I/O functionality of the target hardware unit are specified in a configuration tool. Using the modeling tool, an I/O functionality of the target hardware unit is assigned in the symbol-based program to the signal that is to be assigned. A signal assignment information item is generated in the modeling tool from this assignment. The signal assignment information item is transmitted from the modeling tool to the configuration tool, and the configuration tool takes over the assignment to the I/O functionality of the target hardware unit of the signal to be assigned of the symbol-based program according to the signal assignment information item.

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract: A computer-implemented method for managing at least one data element in control unit development, the method allows uniform management of data elements over the entire development process by providing a management unit having a user interface, associating the data element with the management unit, and associating an access configuration with the management unit. The access configuration defines the accessibility of the data element by a user via the user interface.

Abstract: An encryption method is provided that has a software model of a technical system, the model including software components is encrypted by a public key and a decryption structure, wherein the latter includes definitions of component groups of the software model. The decryption structure is integrated at least partially into the encrypted software model. Correspondingly, in a decryption method according to the invention, via a secret key that likewise comprises definitions of component groups, only the particular component groups are decrypted whose definitions the secret key includes in agreement with the definitions of the encrypted software model. The definitions of the secret key can be extended after the fact by a key extension, so that additional component groups can be decrypted with an extended secret key.

Abstract: A method for executing a first application program of a first control unit on a computer, wherein functions for controlling actuators and/or sensors and/or functions for processing and/or providing data from actuators and/or sensors are executed by the first application program. A first interface between a control unit hardware and a first application program of the control unit is established by the control unit operating system. A first virtual control unit operating system and a first virtual application program are generated by compilation. A simulation environment interface is made available by the simulation environment for transfer of a data item and/or of an event to the first virtual application program and/or the virtual control unit operating system. The simulation environment initiates and controls an execution of the first virtual application program within the control unit operating system within the first virtual machine through the simulation environment interface.

Abstract: A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.

Abstract: A method for connecting an input/output interface of a testing device equipped for testing a control unit to a model of a technical system present in the testing device. The interface connects the control unit to be tested or connects a technical system to be controlled, and the model to be connected to the input/output interface is a model of the technical system to be controlled or a model of the control unit to be tested. The testing device has a plurality of input/output functions connected to the model. The method has provides an interface hierarchy structure and a function hierarchy structure. The method has an automatic configuration of compatible connections between the interface hierarchy structure and the function hierarchy structure so that the model present in the testing device communicates through at least a part of the compatible connections with the control unit to be tested or the technical system to be controlled.

Abstract: A computer-implemented method for generating control unit program code. The control unit program code or an intermediate representation in the generation of the control unit program code is generated from at least one first data object with at least one first software tool. The first software tool outputs at least one message about the generation process during the generation of the control unit program code or the intermediate representation, and a computer-implemented message management environment acquires the message output by the software tool. The evaluation of the messages output by the software tools during the generation process is achieved in a more effective manner in that a qualification for the acquired message at least as open or approved is acquired by the message management environment and in that a qualification precondition for a message qualified as approved is also acquired by the message management environment.

Abstract: A method for manipulating a memory operation of a control unit program on a memory of a virtual or real electronic control unit (ECU), such as is used in vehicles, for example. The manipulation of the memory operation is accomplished by a memory manipulation program component, via which a set of manipulation functions is provided, from which at least one manipulation function is selected, so that this function, by activating the memory manipulation program component, changes a memory access initiated by the control unit program in accordance with the selected manipulation function during execution of the control unit program.

Abstract: A method for the computer-aided generation of at least one part of an executable control program, particularly a measuring, control, regulating, and/or calibration program, for controlling a control system having at least one electronic processor unit is provided. The functionality of the control program is described at least partially in at least one graphical model and the graphical model is divided in hierarchical levels into submodels. A submodel can be divided nested into submodels of a lower hierarchical level, whereby values for options for the compiling of the graphical model to program code are preset and program code is generated from the model co-compiled to the executable control program. Values for options for the compiling of the graphical model to program code and to the executable control program can be preset thereby granularly with the automatic avoidance of conflicting presettings of values for these options.

Abstract: An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

Abstract: A method for interrupting an execution of an overall program of an electronic control unit, wherein the overall program has a first program and a second program. A graphical modeling environment is provided that has graphical model elements, wherein the first program is represented by a first model element, and the second program is represented by a second model element, and the link between the first program and the second program is represented by a third model element. A halt condition is specified by the modeling environment, wherein a program status change leading to interruption of the execution of the overall program is specified by means of the halt condition, the overall program is executed, a program status change is detected during execution of the overall program. The execution of the overall program is interrupted when the program status change specified in the halt condition takes place.

Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

Abstract: A method and a device for testing a control unit, in which sensor data are transmitted over a network connection to a real or simulated control unit, which data are calculated by a data processing system using simulation, in which the simulation of the sensor data takes place at least in part with at least one graphics processor of at least one graphics processor unit of the data processing system. The simulated sensor data are encoded in image data that are output via a visualization interface to a data conversion unit that simulates a visualization unit connected to the visualization interface. Via the data conversion unit the received image data are converted into packet data containing the sensor data through the network connection to the control unit.

Abstract: A development device and a method for creating and testing a control unit program, whereby the preparation of an intervention point for manipulating a quantity of a runtime environment for testing a control unit program component in a test environment having a test scenario program component and an observation device for receiving output values and indicating the test result. An executable program containing all program components is created from one or more program components, including a control unit program component that is to be tested and a test scenario program component. The creation includes generation of a runtime environment, wherein the runtime environment provides a communication channel for transmitting input and output values between the program components, and wherein a component test service is provided that offers an interface to the runtime environment pursuant to the AUTOSAR standard as an intervention point for manipulating a quantity of the runtime environment.

Abstract: A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.