Abstract: A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.

Abstract: A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit.

Abstract: A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors.

Abstract: A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified.

Abstract: A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y?1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m.

Abstract: A triangular wave generating circuit includes: an integrating unit including a capacitor, the integrating unit having an output for providing a triangular wave signal; first and second constant current sources for charging and discharging the capacitor; a switch unit for coupling the first and second current sources to the integrating unit to charge and discharge the capacitor in response to an internal clock signal; a high/low level limiter including first and second comparing units for comparing the output of the integrating unit with upper and lower triangular wave peak limit reference voltages, respectively, and providing output signals indicating when the output of the integrating unit coincides with the peak limit reference voltages; a clock generator for providing the internal clock signal in response to the comparing unit output signals; and means for varying a peak-to-peak swing of the triangular wave signal over time to synchronize the internal clock signal with an externally supplied clock pulse.

Abstract: A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.

Abstract: A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

Abstract: In a voltage reference circuit, a bandgap reference circuit, for generating a bandgap reference voltage and a reference current, includes an operation amplifier, and a first transistor for providing the reference current. Another transistor mirrors the reference current to provide a first current. A compensation controller converts a node voltage from the bandgap reference circuit into a second current and performs current subtraction on the first current and the second current to provide a compensation feedback current to another node of the bandgap reference circuit. So that, second order temperature compensation is performed on the bandgap reference voltage.

Abstract: A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.

Abstract: A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

Abstract: A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.

Abstract: A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.

Abstract: A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.

Abstract: A gate driver for switching power MOSFET including a MOS pair, a first conduction path, and a second conduction path is disclosed. The MOS pair electrically coupling gate of the power MOSFET, for controlling turning on or turning off the power MOSFET. The first conduction path electrically couples to gate of the power MOSFET and the MOS pair, and has a constant resistance. The second conduction path electrically coupling to gate of the power MOSFET and the MOS pair, having variable resistance corresponding to gate voltage of the power MOSFET.

Abstract: An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.

Abstract: A FLASH memory device is provided including a plurality of first floating gates formed over a gate oxide layer formed over a substrate, the first group of floating gates being formed using a selected photolithography process associated with a minimum line width; a second group of floating gates including a plurality of second floating gates, wherein the first and second floating gates are disposed in series, with individual ones of the second floating gates disposed between respective ones of the first floating gates; a plurality of spacers, individual ones of the spacers disposed between adjacent ones of the first and second floating gates; a plurality of control gates associated with the floating gates, wherein the spacers and/or the second floating gates have widths less than the minimum line width.

Abstract: A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage.

Abstract: A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.

Abstract: A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.