Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A program method for a flash memory semiconductor device includes the steps of providing a bit line voltage for programming a group of memory cells and detecting if the bit line voltage meets a selected target voltage. When the bit line voltage meets the selected target voltage, a program operation is performed on the group of memory cells. When the bit line voltage does not meet the selected target voltage, the programming operation is individually performed on at least a first subgroup of memory cells from the group and a second subgroup of memory cells from the group.

Abstract: A voltage regulator as a stable power supply to internal circuits in a semiconductor memory device is provided. This regulator includes a comparing unit, a first driver transistor, a feedback unit, an auxiliary control unit, a first switch, a second switch, and a second driver transistor. The comparing unit compares a reference voltage with a feedback signal to control the first driver transistor and maintain the internal power supply at a stable level. The second driver transistor, controlled by the first and second switches responsive to a trigger signal corresponding abrupt current consumptions and the auxiliary control unit responsive to the comparing result, supplies sufficient and appropriate current to the internal circuits and prevents the internal power supply from excessive overshoot and drop-out.

Abstract: A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control a second PMOS transistor, a third amplifier having a third current source and comparing a third voltage with the precharge voltage to control a first NMOS transistor, and a fourth amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage feedbacks from an output node connected between the second PMOS transistor and the first NMOS transistor.

Abstract: An amplifier includes a first comparator, a second comparator, and an output switch. The first and second comparators respectively compare a pair of differential signals with a half-swing modulation signal to generate first and second pulse-width-modulation (PWM) control signals, wherein a voltage swing of the half-swing modulation signal is smaller than voltage swing of the differential signals. The output switch includes a pair of inputs coupled to receive the PWM control signals to provide a ternary encoded output signal in response to the PWM control signals.

Abstract: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract: A circuit for providing a reference voltage includes a bandgap reference circuit, the bandgap reference circuit providing a first reference voltage and a data storage. The data storage stores a digital value corresponding to the first reference voltage. A digital to analog converter is coupled to the data storage for providing a second reference voltage corresponding to the digital value. The circuit also includes an output switch circuit responsive to at least one control signal, the output switch circuit providing either the first reference voltage or the second reference voltage to an output node responsive to the control signal.

Abstract: An amplifier includes a first comparator, a second comparator, and an output switch. The first and second comparators respectively compare a pair of differential signals with a half-swing modulation signal to generate first and second pulse-width-modulation (PWM) control signals, wherein a voltage swing of the half-swing modulation signal is smaller than voltage swing of the differential signals. The output switch includes a pair of inputs coupled to receive the PWM control signals to provide a ternary encoded output signal in response to the PWM control signals.

Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A clock circuit for generating a spread spectrum clock signal with reduced amplitude electromagnetic interference (EMI) spectral components is provided where the clock circuit includes a delay line circuit, the delay line circuit providing a spread spectrum clock signal from a reference clock signal in response to a modulation signal, a delay of said delay line circuit being controlled by said modulation signal.

Abstract: A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that corresponds to the at least one normal cell are provided with a constant current. Second, the erasing threshold voltage of the at least one normal cell is determined, and then the at least one normal cell is erased to be of the erasing threshold voltage. By virtue of adding the constant current, the higher erasing threshold voltage can be acquired, and in consequence over-erase can be avoided.

Abstract: A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device.

Abstract: A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.

Abstract: A power output device includes a bridged output stage, a reference voltage generator and a detecting unit to compare the output voltages from the aforementioned two units. The bridged output stage may be implemented by a full-bridge or a half-bridge configuration. The reference voltage generator is symmetric to the bridged output stage to generate a reference voltage, which is served as a reference voltage range for the voltage difference of the two terminals of the turned-on transistors in the bridged output stage during operation. When the detecting unit detects the voltages across the two terminals of the turned-on transistors in the bridged output stage exceed the reference voltage range, all the transistors are turned off and no power is outputted to the load. Therefore, the circuit is capable of preventing damages caused by a large current due to overload or short circuit.

Abstract: An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

Abstract: A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the FLASH memory device, the word lines being spaced from each other a distance less than a minimum feature size which can be imaged by a selected photolithography process used in forming at least a portion of the mask layer pattern, and etching the control gate polysilicon layer through the mask layer.