Abstract: A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.

Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.

Abstract: A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6.

Abstract: An electrical fuse comprises first, second, and third thick oxide NMOS transistors and a thin oxide NMOS transistor. The first thick oxide NMOS transistor has a gate connected to a first input signal, and the thin oxide NMOS transistor has a drain connected to the source of the first thick oxide NMOS transistor and a gate shorted to its source. The second thick oxide transistor has a gate connected to a power up signal, a drain connected to the source of the thin oxide NMOS transistor, and a source connected to a reference voltage. The third thick oxide transistor has a gate connected to the second input signal, a drain connected to a high voltage, and a source connected to the drain of the thin oxide NMOS transistor. The first input signal and the second input signal are complementary.

Abstract: A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.

Abstract: An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.

Abstract: A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k?1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.

Abstract: A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.

Abstract: A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.

Abstract: A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.

Abstract: A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source.

Abstract: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value.

Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.

Abstract: A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.

Abstract: A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.