Abstract: Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.

Abstract: Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

Abstract: Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.

Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Abstract: A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.

Abstract: A semiconductor device includes a plurality of drain lines each being commonly connected to first nodes of a plurality of memory cells, a plurality of bit lines respectively connected to second nodes of the memory cells, a source line, a transistor that connects the drain lines to the source line, and a transistor that connects the source line to a ground potential in response to an access to the memory cell. Under control in which the memory cells are all deactivated, the semiconductor device controls the drain line to a drain potential that is higher than the ground potential, and controls the source line to be in a floating state by deactivating the transistors.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract: To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.

Abstract: A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip.

Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

Abstract: A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid.