Patents Assigned to Elpida Memory, Inc.
  • Semiconductor device and method of forming the same
    Patent number: 8558298
    Abstract: A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: October 15, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takashi Shinhara
  • Method of exposing a semiconductor wafer and exposure apparatus
    Patent number: 8558990
    Abstract: An exposure method includes the following processes. An autofocus scan process is performed to detect a defocused portion of a first resist film over a semiconductor wafer and to generate a detection signal that indicates the defocused portion detected. A first exposure scan process is performed while selectively blinding the first resist film, with reference to a detection signal related to the defocused portion detected.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: October 15, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masayoshi Danbata, Hisanori Ueno
  • SEMICONDUCTOR DEVICE, DESIGNING METHOD THEREFOR, AND MANUFACTURING METHOD THEREFOR
    Publication number: 20130264655
    Abstract: In a semiconductor device including active regions which are adjacent to each other with an element isolation region interposed therebetween and which are different in height from the element isolation region, when a contact is formed in a gate wiring on the element isolation region, a contact failure is caused. Provided is a semiconductor device including an element isolation region, two active regions adjacent to each other with the element isolation region interposed therebetween and having surfaces which are higher than that of the element isolation region, a gate wiring commonly led from the respective active regions and extending through the element isolation region, and a contact for connecting the gate wiring to a conductor layer above the gate wiring. The contact is provided in a region other than the element isolation region, or is provided in an expanded element isolation region.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Takeshi KISHIDA
  • SEMICONDUCTOR DEVICE HAVING PLURAL DATA INPUT/OUTPUT TERMINALS
    Publication number: 20130265831
    Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Teppei MIYAJI, Yoshinori MATSUI
  • SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING
    Publication number: 20130265840
    Abstract: Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Masaki YOSHIMURA, Hisayuki NAGAMINE
  • SEMICONDUCTOR DEVICE HAVING FIN-SHAPED FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    Publication number: 20130264621
    Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroo NISHI, Hiromitsu OSHIMA
  • Method and system of evaluating distribution of lattice strain on crystal material
    Patent number: 8552372
    Abstract: A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiro Nojima
  • Semiconductor device having ring-shaped gate electrode, design apparatus, and program
    Patent number: 8552510
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takamitsu Onda
  • Method of manufacturing semiconductor device
    Patent number: 8551884
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Katsuhiko Tanaka
  • Semiconductor device having point-shift type FIFO circuit
    Patent number: 8553489
    Abstract: For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Yuuji Motoyama
  • Internal power supply circuit, semiconductor device, and manufacturing method of semiconductor device
    Patent number: 8553487
    Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Koichiro Hayashi
  • Nonvolatile semiconductor memory device and memory system having the same
    Patent number: 8553459
    Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Naoharu Shinozaki, Masao Taguchi, Takahiro Hatada, Satoru Sugimoto, Satoshi Sakurakawa
  • DEVICE
    Publication number: 20130256918
    Abstract: A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.
    Type: Application
    Filed: March 12, 2013
    Publication date: October 3, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Atsushi TOMOHIRO
  • METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY
    Publication number: 20130258780
    Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Osama Khouri, Simone Bartoli
  • SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER SUPPLY VOLTAGE
    Publication number: 20130258792
    Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Tomohiro KITANO, Hisayuki NAGAMINE
  • SEMICONDUCTOR DEVICE
    Publication number: 20130256788
    Abstract: A semiconductor device comprises an isolation region formed by filling a trench with an insulator, an active region surrounded with the sidewall of the trench, a combined pillar including a semiconductor pillar in the active region and an insulator pillar in the isolation region, a gate electrode covering a side surface surrounding the combined pillar; and a transistor including the combined pillar and the gate electrode. The trench has a sidewall in a semiconductor substrate. The insulator pillar contacts the semiconductor pillar with the sidewall of the trench interposed therebetween.
    Type: Application
    Filed: March 7, 2013
    Publication date: October 3, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yu KOSUGE
  • SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER-SUPPLY VOLTAGE
    Publication number: 20130257175
    Abstract: The semiconductor device includes a capacitance element connected to a first power-supply line via a first switch element, and to a second power-supply line via a second switch element; and a control circuit that controls the first and second switch elements. The control circuit turns the first switch element ON during a first period (voltage is supplied only to the first power-supply line), while turning the second switch element ON during a second period (voltage is supplied to both the first and second power-supply lines).
    Type: Application
    Filed: March 11, 2013
    Publication date: October 3, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kazuhiro YOSHIDA
  • SEMICONDUCTOR DEVICE
    Publication number: 20130258793
    Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Shinichi TAKAYAMA, Akira KOTABE, Kiyoo ITOH, Tomonori SEKIGUCHI
  • SEMICONDUCTOR DEVICE HAVING PLURAL CHIP CONNECTED TO EACH OTHER
    Publication number: 20130258788
    Abstract: Disclosed herein is a device that includes: a first timing adjustment circuit generating a first control signal based on a command and an output buffer outputting a plurality of data sets in a serial at a timing based on the first control signal; and a second semiconductor chip including: a plurality of holding circuits holding the data sets in parallel, a second timing adjustment circuit generating a second control signal based on the command, and an input buffer sequentially capturing the data sets supplied from the holding circuits based on the second control signal.
    Type: Application
    Filed: March 18, 2013
    Publication date: October 3, 2013
    Applicant: c/o Elpida Memory, Inc.
    Inventors: Akira Ide, Naoki Ogawa
  • Semiconductor apparatus and its control method
    Patent number: 8547770
    Abstract: Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First logic circuit is disposed between first sub power supply line and second power supply line and comprises first input node and second input node receiving second signal and third signal respectively, and output node. First logic circuit outputs an active voltage associated with a logical level of second signal to output node in active state, and outputs a standby voltage associated with a voltage of second power supply line to output node regardless of the logical level of second signal in non-active state.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kohei Nakamura, Sachiko Kamisaki