Patents Assigned to Elpida Memory, Inc.
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Patent number: 8531010Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.Type: GrantFiled: November 3, 2010Date of Patent: September 10, 2013Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Kazuhiro Nojima
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Publication number: 20130228898Abstract: Disclosed herein is a device that includes: a first semiconductor chip having a first internal circuit formed in a first substrate; and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode.Type: ApplicationFiled: February 28, 2013Publication date: September 5, 2013Applicant: Elpida Memory, Inc.Inventor: Akira IDE
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Publication number: 20130228837Abstract: A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to ?700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film.Type: ApplicationFiled: February 27, 2013Publication date: September 5, 2013Applicant: Elpida Memory, Inc.Inventors: Mitsunari SUKEKAWA, Takayuki MATSUI
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Publication number: 20130228935Abstract: Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.Type: ApplicationFiled: March 5, 2013Publication date: September 5, 2013Applicant: Elpida Memory, Inc.Inventors: Yoshimi Terui, Kazuhiko Matsuki
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Publication number: 20130229870Abstract: A semiconductor random access memory device includes a memory cell including a resistor whose resistance varies by formation and disappearance of a filament due to an oxidation-reduction reaction of metal ions, a memory area configured to include a first memory area operable in a nonvolatile mode in which a stored content thereof is not lost by a power-off event, and a second memory area operable in a volatile mode in which the stored content thereof is lost by the power-off event, each of the first memory area and the second memory area including the plurality of the memory cells, a register circuit that stores information including a first address information indicating the first memory area, and a second address information indicating the second memory area, and a control circuit that controls the nonvolatile mode, and the volatile mode, with reference to the information stored in the register circuit.Type: ApplicationFiled: April 12, 2013Publication date: September 5, 2013Applicant: Elpida Memory, Inc.Inventor: Kazuhiko KAJIGAYA
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Patent number: 8525563Abstract: Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system.Type: GrantFiled: September 12, 2012Date of Patent: September 3, 2013Assignee: Elpida Memory, Inc.Inventor: Yutaka Uemura
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Patent number: 8527820Abstract: A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other.Type: GrantFiled: February 7, 2011Date of Patent: September 3, 2013Assignee: Elpida Memory, Inc.Inventor: Shin Ito
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Patent number: 8525578Abstract: Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.Type: GrantFiled: January 25, 2012Date of Patent: September 3, 2013Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20130223170Abstract: A semiconductor memory device comprises: plurality of global bit lines; plurality of sense amplifier circuits each connected to corresponding one of the plurality of global bit lines; plurality of column selection lines each of which is connected to or disconnected from corresponding one of the plurality of sense amplifier circuits according to column address information; and plurality of local bit lines including first local bit line and second local bit line. The first local bit line is connected to or disconnected from corresponding one of the plurality of global bit lines according to first row address information different from column address information. The second local bit line replaces first local bit line when defect is present in first local bit line and is connected to or disconnected from corresponding global bit line according to second row address information different from column address information.Type: ApplicationFiled: February 25, 2013Publication date: August 29, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130223167Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,Type: ApplicationFiled: March 15, 2013Publication date: August 29, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130227229Abstract: A semiconductor device includes a command terminal, a plurality of memory banks, a control circuit and an output circuit. The control circuit is configured to respond to each of issuance of a read command, that is supplied to the command terminal, to perform a read operation on any one of the memory banks so that the any one of the memory banks output a plurality of read data sets. The output circuit receives the read data sets and outputs the read data sets to outside in response to a clock signal so that a first interval substantially the same as a period of the clock signal or longer than the period of the clock signal is interposed between the read data sets.Type: ApplicationFiled: February 21, 2013Publication date: August 29, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Patent number: 8520449Abstract: A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.Type: GrantFiled: September 9, 2011Date of Patent: August 27, 2013Assignee: Elpida Memory, Inc.Inventor: Kazuhiko Kajigaya
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Patent number: 8519514Abstract: A semiconductor device includes a substrate, at least one via hole provided on the substrate, a through silicon via provided in the at least one via hole, and an interface chip that is electrically connected to the core chips through the through silicon via. The via hole includes a bowing shaped portion in which a diameter of a center portion is larger than diameters of both edges.Type: GrantFiled: October 5, 2010Date of Patent: August 27, 2013Assignee: Elpida Memory, Inc.Inventor: Seiya Fujii
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Publication number: 20130215659Abstract: A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer.Type: ApplicationFiled: March 18, 2013Publication date: August 22, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130215691Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.Type: ApplicationFiled: March 15, 2013Publication date: August 22, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130215698Abstract: A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.Type: ApplicationFiled: February 14, 2013Publication date: August 22, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130214338Abstract: A semiconductor device comprises a convex portion, a concave portion provided so as to cover upper and side surfaces of the convex portion, a gate electrode provided so as to be opposed to the convex portion with a gate insulating film interposed between the gate electrode and the convex portion, a pair of diffusion layers provided within the convex portion so as to sandwich the gate electrode, and a contact plug provided on the concave portion, so as to be electrically connected to at least one of the diffusion layers.Type: ApplicationFiled: January 3, 2013Publication date: August 22, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Patent number: 8513993Abstract: To include a phase-difference-amount detecting circuit that detects an amount of phase difference between an external clock signal and a replica clock signal, a variable delay circuit that delays the external clock signal based on the amount of phase difference to generate an internal clock signal, and a replica buffer that delays the internal clock signal to generate the replica clock signal. According to the present invention, the variable delay circuit is controlled based on the amount of phase difference, instead of being controlled based on whether the phase of the replica clock signal is advanced or delayed with respect to the external clock signal. Accordingly, even when the amount of phase difference is large, a DLL circuit can be locked at a high speed.Type: GrantFiled: June 16, 2010Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventor: Hiroki Takahashi
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Patent number: 8513638Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.Type: GrantFiled: September 2, 2011Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventors: Tomoyasu Kakegawa, Isamu Asano, Tsuyoshi Kawagoe, Hiromi Sasaoka, Naoya Higano, Yuta Watanabe
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Patent number: 8513121Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.Type: GrantFiled: September 15, 2012Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata