Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A semiconductor device includes an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film. A first sidewall film is formed in the air gap part so that the first sidewall film contacts with the side surface of the wiring.

Abstract: A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.

Abstract: Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.

Abstract: Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level.

Abstract: In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.

Abstract: A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.

Abstract: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.

Abstract: A semiconductor device includes a first memory cell, a first line, a second line and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.

Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.

Abstract: A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.

Abstract: A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and forming an upper electrode comprising titanium nitride on the first protective film. The method can include a step of forming a second protective film on the lower electrode before the step of forming the dielectric film on the lower electrode.

Abstract: A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.

Abstract: A semiconductor device includes a first circuit that generates a self refresh signal in a predetermined cycle asynchronous with a cycle set externally, a second circuit that generates a refresh address in response to the self refresh signal and updates the refresh address and outputs the refresh address, a third circuit that retains a relief address, a fourth circuit that counts number of generation of the self refresh signal and activates an interrupt signal when a count of the number of generation reaches a predetermined count, a fifth circuit that specifies the refresh address when the interrupt signal is in an inactive state and specifies the relief address when the interrupt signal is in an active state, and a sixth circuit that performs a refresh operation on memory cells specified by the selected refresh address or the relief address. The second circuit temporarily stops updating the refresh address in response to activation of the interrupt signal.

Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.