Patents Assigned to Elpida Memory, Inc.
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Patent number: 8504964Abstract: A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.Type: GrantFiled: June 5, 2009Date of Patent: August 6, 2013Assignee: Elpida Memory, Inc.Inventors: Hayato Ooishi, Kazuhiko Matsuki
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Patent number: 8502395Abstract: A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.Type: GrantFiled: March 7, 2012Date of Patent: August 6, 2013Assignee: Elpida Memory, Inc.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 8503253Abstract: A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.Type: GrantFiled: October 9, 2012Date of Patent: August 6, 2013Assignee: Elpida Memory, Inc.Inventor: Shuichi Tsukada
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Publication number: 20130194857Abstract: Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals.Type: ApplicationFiled: January 23, 2013Publication date: August 1, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130193590Abstract: A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: Elpida Memory, Inc.Inventors: Simone Bartoli, Antonino Geraci, Stefano Sivero, Marco Passerini
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Publication number: 20130193507Abstract: A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Applicant: Elpida Memory, Inc.Inventors: Soichiro YOSHIDA, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe
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Patent number: 8497576Abstract: A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2, semiconductor chip 3a stacked on substrate 4 together with semiconductor chip 2, and having a foot print larger than semiconductor chip 2, through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2, through electrode 32 extending through semiconductor chip 3a at a position facing to through electrode 22, and conduction bump 7b arranged between through electrode 22 and through electrode 32, and conductively connecting through electrode 22 with through electrode 32.Type: GrantFiled: October 1, 2012Date of Patent: July 30, 2013Assignee: Elpida Memory, Inc.Inventor: Seiya Fujii
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Patent number: 8498831Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.Type: GrantFiled: October 8, 2010Date of Patent: July 30, 2013Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Hideyuki Yoko, Kayoko Shibata, Kenichi Tanamachi, Takanori Eguchi, Yasuyuki Shigezane, Naoki Ogawa, Kazuo Hidaka
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Patent number: 8499272Abstract: A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.Type: GrantFiled: March 29, 2012Date of Patent: July 30, 2013Assignee: Elpida Memory, Inc.Inventor: Toshinao Ishii
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Publication number: 20130187294Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: ApplicationFiled: January 14, 2013Publication date: July 25, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Patent number: 8493132Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: GrantFiled: March 20, 2008Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Patent number: 8492814Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.Type: GrantFiled: August 23, 2012Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Hiroyuki Fujimoto, Shinpei Iijima
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Patent number: 8493110Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.Type: GrantFiled: July 15, 2011Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Yoshio Mizukane, Hiroki Fujisawa
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Patent number: 8493137Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.Type: GrantFiled: September 16, 2011Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Marco Passerini, Francesco Mannino, Chiara Missiroli
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Patent number: 8493807Abstract: A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch.Type: GrantFiled: October 31, 2012Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventor: Seiji Narui
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Publication number: 20130181345Abstract: Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.Type: ApplicationFiled: January 8, 2013Publication date: July 18, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130182516Abstract: A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.Type: ApplicationFiled: January 16, 2013Publication date: July 18, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Patent number: 8486831Abstract: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.Type: GrantFiled: November 23, 2011Date of Patent: July 16, 2013Assignee: Elpida Memory, IncInventor: Hirotaka Kobayashi
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Patent number: 8486808Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode material that covers a gate insulating film formed on each of side surfaces of first and second silicon pillars, wherein a film formation amount of the gate electrode material is controlled so that a first part with which the side surface of the first silicon pillar is covered via the gate insulating film does not contact with a second part with which the side surface of the second silicon pillar is covered via the gate insulating film. The method further includes: forming a mask insulating film that covers the first and second parts and fills a region between the first and second parts; and etching the gate electrode material using the mask insulating film as a mask, thereby forming gate electrodes with which the side surfaces of the first and second silicon pillars are covered via the gate insulating film, respectively and a conductive film electrically connecting the gate electrodes to each other.Type: GrantFiled: April 20, 2011Date of Patent: July 16, 2013Assignee: Elpida Memory, Inc.Inventor: Kazuhiro Nojima
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Patent number: 8486780Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.Type: GrantFiled: August 29, 2011Date of Patent: July 16, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Hiroyuki Ode