Abstract: A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters.

Abstract: A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a signal that is supplied to the command address terminal. According to the present invention, it is possible to perform a test that uses non-compressed actual data while allocating plural data input/output terminals to one determination circuit within a tester. With this configuration, it is possible to test a large number of semiconductor devices in parallel by using a limited number of determination circuits within the tester.

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

Abstract: Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a third insulation film and the lower pillar is covered with a first insulation film, which is a gate insulation film, from a side surface thereof to the second insulation film. A gate electrode is insulated from an upper conductive layer by the second and third insulation films.

Abstract: To provide an output driver that outputs read data to outside and a mode register that sets a swing capability of the output driver. A transition start timing of the read data driven by the output driver is made relatively earlier when a swing capability of the output driver set by the mode register is set to be relatively large, and the transition start timing is relatively delayed when the swing capability of the output driver set by the mode register is set to be relatively small. With this configuration, a timing when the read data exceeds a threshold level can be caused to coincide with a desired timing regardless of the swing capability of the output driver.

Abstract: A voltage level shift circuit in which a difference in response characteristic depending on the signal level of an input signal is suppressed. The voltage level shift circuit generates an output signal VOUT having a voltage amplitude different from that of the input signal. An inverter INV2 generates a voltage V1 in the range of VSS to VDDI according to the input signal. An inverter INV3 generates a voltage V2 in the range of VSS to VPERI according to the input signal. An inverter INV4 generates the output signal VOUT according to V1 and V2.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A nonvolatile RAM for reading and writing data in a random manner includes a memory area configured by a plurality of memory cells suited to a nonvolatile-mode write operation, in which the stored content thereof is not lost irrespective of a power-off event, and a volatile-mode write operation, in which the stored content thereof is lost in the power-off event. A register designates a first portion of the memory area adapted to the nonvolatile-mode write operation regarding fixed data such as program codes and a second portion of the memory area serving as a work area adapted to the volatile-mode write operation. A control circuit performs the nonvolatile-mode write operation on the first portion of the memory area while performing the volatile-mode write operation on the second portion of the memory area.

Abstract: A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

Abstract: A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power line.

Abstract: A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar.

Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

Abstract: The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.

Abstract: There are provided: a silicon pillar that is formed almost perpendicularly to a main surface of a substrate; first and second impurity diffused layers that are arranged in a lower part and an upper part of the silicon pillar, respectively; a gate electrode that is arranged horizontally through the silicon pillar; and a gate insulating film that is arranged between the gate electrode and the silicon pillar. The silicon pillar consequently has a small volume, which makes it possible to reduce the leak current of the transistor or thyristor formed in the silicon pillar.

Abstract: Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.