Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract: A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Abstract: Disclosed herein is a semiconductor device that includes a clock terminal supplied with a first clock signal from outside; a dividing circuit dividing a frequency of the first clock signal to generate a plurality of second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal, the multiplexer having a predetermined operating delay time; a data strobe terminal supplied with a first data strobe signal from outside; a strobe signal generation circuit adding the predetermined operating delay time to the first data strobe signal to generate a second data strobe signal; and a skew detection circuit measuring a skew between the third clock signal and the second data strobe signal.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.

Abstract: A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.

Abstract: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.

Abstract: Disclosed herein is a device that includes at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising a first switch circuit and a first driver circuit driving the first switch circuit to be turned ON or OFF, the first switch circuit including a first node coupled to the selection voltage source line, a second node coupled to the selection/non-selection voltage receiving line of the first memory plane and a third node coupled to the selection/non-selection voltage receiving line of the second memory plane, and the first driver circuit being provided in common to the first and second memory planes.

Abstract: A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid.

Abstract: A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region.

Abstract: A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M?2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M?1)-th penetration electrodes of the first semiconductor chip, respectively.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.

Abstract: A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid.

Abstract: A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the device to cause the device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the device to cause the device to return to the controller a data signal.

Abstract: Disclosed herein is a semiconductor chip that includes: a semiconductor chip body including a semiconductor substrate and a circuit element layer provided on a main surface of the semiconductor substrate, the circuit element layer including a plurality of circuit elements; first to fourth penetrating electrodes penetrating the semiconductor chip body; a first conductive path electrically connected between the first penetrating electrode and the second penetrating electrode without being in contact with any one of the circuit elements; a second conductive path electrically connected between the first penetrating electrode and the third penetrating electrode without being in contact with any one of the circuit elements; and a third conductive path electrically connected between the second penetrating electrode and the fourth penetrating electrode without being in contact with any one of the circuit elements.

Abstract: A semiconductor device includes an inverter constituted from first and second transistors connected in series between a first power supply and a second power supply and a first circuit connected between the first and second transistors which have gates coupled together. The first circuit includes a first resistance element of a positive temperature characteristic and a third transistor connected to each other in parallel. The third transistor operates at least in a region where a resistance between drain and source terminals exhibits a negative temperature characteristic.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.