Patents Assigned to Endicott Interconnect Technologies, Inc.
  • Plating method for circuitized substrates
    Patent number: 7169313
    Abstract: A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: January 30, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Robert D. Edwards, John J. Konrad, Roy H. Magnuson, Timothy L. Wells, Michael Wozniak
  • Method of making circuitized substrate
    Patent number: 7163847
    Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: January 16, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
  • Method of making a circuitized substrate with sintered paste connections and multilayered substrate assembly having said substrate as part thereof
    Publication number: 20070006452
    Abstract: A method of making a circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Frank Egitto, Voya Markovich, Luis Matienzo
  • Circuitized substrate with soler-coated microparticle paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same and method of making said substrate
    Publication number: 20070007033
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a binder component and at least one metallic component including microparticles. In another embodiment, the paste includes the binder and a plurality of nano-wires. Selected ones of the microparticles or nano-wires include a layer of solder thereon. A method of making such a substrate is also provided, as are an electrical assembly and information handling system adapter for having such a substrate as part thereof.
    Type: Application
    Filed: October 6, 2005
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra Das, John Lauffer, Roy Magnuson, Voya Markovich
  • Imaging inspection apparatus with directional cooling
    Publication number: 20070009084
    Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure for directing cooling fluid (e.g., air) toward and over the devices, the structure including a fan for directing cooling fluid in a first direction and a plurality of fluid deflectors for deflecting at least part of the fluid toward respective ones of the devices.
    Type: Application
    Filed: June 1, 2005
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar Bhatt, Varaprasad Calmidi, James McNamara, Sanjeev Sathe
  • Method of making a capacitive substrate using photoimageable dielectric for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate
    Publication number: 20070010064
    Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.
    Type: Application
    Filed: February 13, 2006
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra Das, John Lauffer, How Lin, Voya Markovich
  • Method of making a capacitive substrate for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate
    Publication number: 20070010065
    Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.
    Type: Application
    Filed: February 13, 2006
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra Das, John Lauffer, How Lin, Voya Markovich
  • Circuitized substrate with sintered paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same
    Publication number: 20070007032
    Abstract: A circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Frank Egitto, Voya Markovich, Luis Matienzo
  • Stacked chip electronic package having laminate carrier and method of making same
    Patent number: 7161810
    Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 9, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Lawrence R. Fraley, Voya Markovich
  • Circuitized substrate with split conductive layer, method of making same, electrical assembly utilizing same, and information handling system utilizing same
    Patent number: 7157646
    Abstract: A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Circuitized substrate with filled isolation border, method of making same, electrical assembly utilizing same, and information handling system utilizing same
    Patent number: 7157647
    Abstract: A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Method of making high speed circuit board
    Patent number: 7152319
    Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same
    Publication number: 20060284304
    Abstract: A wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow. A method of making the package is also provided, as is an information handling system (e.g., computer) adapted for utilizing such packages.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: David Caletka, Varaprasad Calmidi, Sanjeev Sathe
  • Imaging inspection apparatus with improved cooling
    Publication number: 20060274891
    Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) positioned on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure to provide cooling to the imaging devices.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 7, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar Bhatt, Varaprasad Calmidi, James McNamara, Sanjeev Sathe
  • Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
    Patent number: 7145221
    Abstract: A circuitized substrate comprising a first layer comprised of a dielectric material including a low moisture absorptive polymer resin in combination with a nodular fluoropolymer web encased within the resin, the resulting dielectric layer formed from this combination not including continuous or semi-continuous fibers as part thereof. The substrate further includes at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: December 5, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Irving Memis, Kostas I. Papathomas
  • Radio frequency device for tracking goods
    Patent number: 7142121
    Abstract: A radio frequency (RF) device (or “tag”) for containing specific information relating to a particular good being shipped from one location (e.g., warehouse) to another (e.g., customer). The device includes a circuitized substrate (e.g., a printed circuit board), a semiconductor chip, an antenna and a power regulator, and is designed in one embodiment to be partly inserted within a good (e.g., a cardboard box) containing one or more of the goods being shipped and tracked. Alternatively, the device may be attached by other means (e.g., adhesive). A shipper can simply track the goods containing such devices using wireless communication devices (e.g., satellites) to quickly and readily ascertain the specific location of the goods at any time as well as the appropriate desired information relating to such goods (e.g., quantity, weight, type, etc.).
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 28, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, William Kimler, How Lin, William Maines, Voya Markovich
  • Plating method for circuitized substrates
    Publication number: 20060255009
    Abstract: A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 16, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Norman Card, Robert Edwards, John Konrad, Roy Magnuson, Timothy Wells, Michael Wozniak
  • Multi-chip electronic package with reduced line skew, method of making same and information handling system utilizing same
    Publication number: 20060255460
    Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventor: Irving Memis
  • Method of making circuitized substrate with filled isolation border
    Publication number: 20060248717
    Abstract: A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 9, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: John Lauffer, James Larnerd, Voya Markovich
  • Substrate test apparatus and method of testing substrates
    Patent number: 7129732
    Abstract: A test apparatus for testing circuitized substrates such as PCB test coupons for thru-hole failure in which the substrate may be cooled to a temperature less than the ambient temperature surrounding the test apparatus housing in which the testing is accomplished. A method of testing substrates is also provided.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 31, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventor: Kevin T. Knadle