Abstract: An x-ray source assembly capable of producing x-rays suitable for use in medical, explosive detection, and other areas. The assembly includes a housing having a two-part socket member (which holds the assembly's x-ray tube therein) positioned therein. The two-part housing defines an opening through with the tube's x-rays are emitted.
Type:
Application
Filed:
August 16, 2006
Publication date:
February 21, 2008
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Fletcher L. Chapin, Liza M. Hart, Allan O. Johnson
Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
Type:
Grant
Filed:
October 5, 2005
Date of Patent:
February 19, 2008
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Elizabeth Foster, Gregory Kevern, Anita Sargent
Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.
Type:
Grant
Filed:
May 12, 2005
Date of Patent:
February 19, 2008
Assignee:
Endicott Interconnect Technologies, Inc.
Abstract: A method of making a circuitized substrate in which the substrate includes circuit elements having exposed surfaces defined by two thin layers of permanent photoimaged solder mask material which are applied through fine mesh screens. The use of two thin layers assures effective coverage of the material to precisely expose the desired surfaces in high-density circuit patterns. A circuitized substrate assembly and an information handling system adapted for having one or more such assemblies therein are also provided.
Type:
Application
Filed:
August 8, 2006
Publication date:
February 14, 2008
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Norman A. Card, Richard A. Day, John J. Konrad
Abstract: Apparatus for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can then be individually bonded to other, like substrates to form a larger multi-layered substrate with a plurality of conductive thru-holes, conductive and dielectric layers as part thereof.
Type:
Grant
Filed:
August 3, 2007
Date of Patent:
February 12, 2008
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, Voya R. Markovich, James W. Orband, William E. Wilson
Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.
Type:
Grant
Filed:
June 12, 2007
Date of Patent:
February 5, 2008
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Subahu D. Desai, How T. Lin, John M. Lauffer, Voya R. Markovich, David L. Thomas
Abstract: A method of making a multilayered circuitized substrate assembly which includes bonding at least two circuitized substrates each including at least one layer of high temperature dielectric material, one of these layers in turn including at least one thru-hole therein having therein a quantity of a a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered during the bonding to form a conductive path through the dielectric of one of the substrates.
Type:
Application
Filed:
September 28, 2007
Publication date:
January 31, 2008
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Frank Egitto, Voya Markovich, Luis Matienzo
Abstract: A photoresist composition, e.g., a positive acting resist, for use in the formation of circuit patterns and the like on printed circuit boards and the like circuitized substrates, the photoresist composition including a quantity of silver therein in a sufficient amount to substantially prevent bacteria formation within said composition. A method of making the composition is also provided.
Type:
Application
Filed:
July 25, 2006
Publication date:
January 31, 2008
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Ross W. Keesler, John J. Konrad, Roy H. Magnuson, Robert A. Sinicki
Abstract: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.
Type:
Application
Filed:
September 27, 2007
Publication date:
January 24, 2008
Applicant:
Endicott Interconnect Technologies, Inc.
Abstract: A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.
Type:
Application
Filed:
June 19, 2006
Publication date:
December 20, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Abstract: A method of making a circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The produced substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer.
Type:
Application
Filed:
August 15, 2007
Publication date:
December 13, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Charles Danoski, Irving Memis, Steven Rosser
Abstract: A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer. The method is extendible to the formation of such substrates, including to the formation of multilayered substrates having many conductive and dielectric layers. Such substrates may include one or more electrical components (e.g., semiconductor chips) mounted thereon and may also be mounted themselves onto other substrates.
Type:
Grant
Filed:
January 9, 2006
Date of Patent:
December 11, 2007
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Frank D. Egitto, Stephen Krasniak, John M. Lauffer, Voya R. Markovich, Luis J. Matienzo
Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
Type:
Application
Filed:
May 23, 2006
Publication date:
November 29, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
Abstract: Apparatus for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can then be individually bonded to other, like substrates to form a larger multi-layered substrate with a plurality of conductive thru-holes, conductive and dielectric layers as part thereof.
Type:
Application
Filed:
August 3, 2007
Publication date:
November 22, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
John Lauffer, Voya Markovich, James Orband, William Wilson
Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can then be individually bonded to other, like substrates to form a larger multi-layered substrate with a plurality of conductive thru-holes, conductive and dielectric layers as part thereof.
Type:
Grant
Filed:
April 21, 2005
Date of Patent:
November 13, 2007
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
John M. Lauffer, Voya R. Markovich, James W. Orband, William E. Wilson
Abstract: A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer.
Type:
Grant
Filed:
September 29, 2004
Date of Patent:
November 13, 2007
Assignee:
Endicott Interconnect Technologies, Inc.
Inventors:
Charles E. Danoski, Irving Memis, Steven G. Rosser
Abstract: An interposer including at least two dielectric layers bonded to each other, sandwiching a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts formed within and protruding from openings with the dielectric layers.
Type:
Grant
Filed:
April 21, 2005
Date of Patent:
November 6, 2007
Assignee:
Endicott Interconnect Technologies, Inc.
Abstract: A method of making a wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow.
Type:
Application
Filed:
July 9, 2007
Publication date:
November 1, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
David Caletka, Varaprasad Calmidi, Sanjeev Sathe
Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.
Type:
Application
Filed:
June 12, 2007
Publication date:
October 25, 2007
Applicant:
Endicott Interconnect Technologies, Inc.
Inventors:
Subahu Desai, How Lin, John Lauffer, Voya Markovich, David Thomas
Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.
Type:
Application
Filed:
April 4, 2006
Publication date:
October 4, 2007
Applicant:
Endicott Interconnect Technologies, Inc.