Patents Assigned to Endicott Interconnect Technologies, Inc.
  • Circuitized substrate with conductive paste, electrical assembly including said circuitized substrate and method of making said substrate
    Publication number: 20070221404
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.
    Type: Application
    Filed: May 23, 2007
    Publication date: September 27, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra Das, Kostas Papathomas, Voya Markovich
  • Dielectric composition for forming dielectric layer for use in circuitized substrates
    Patent number: 7270845
    Abstract: A dielectric composition which forms a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like. As such a layer, it includes a cured resin material and a predetermined percentage by weight of particulate fillers, thus not including continuous fibers, semi-continuous fibers or the like as part thereof.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 18, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert Japp, Kostas Papathomas
  • Method for making a multilayered circuitized substrate
    Publication number: 20070199195
    Abstract: A method of making a multilayered circuitized substrate in which a continuous process is used to form electrically conductive layers which each will form part of a sub-composite. The sub-composites are then aligned such that openings within the conductive layers are also aligned, the sub-composites are then bonded together, and a plurality of holes are then laser drilled through the entire thickness of the bonded structure.
    Type: Application
    Filed: May 2, 2007
    Publication date: August 30, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Thomas Davis, Subahu Desai, John Lauffer, James McNamara, Voya Markovich
  • Imaging inspection apparatus with directional cooling
    Patent number: 7261466
    Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure for directing cooling fluid (e.g., air) toward and over the devices, the structure including a fan for directing cooling fluid in a first direction and a plurality of fluid deflectors for deflecting at least part of the fluid toward respective ones of the devices.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: August 28, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar C. Bhatt, Varaprasad V. Calmidi, James J. McNamara, Jr., Sanjeev Sathe
  • Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion
    Publication number: 20070182016
    Abstract: A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof.
    Type: Application
    Filed: April 5, 2007
    Publication date: August 9, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert Japp, Irving Memis, Kostas Papathomas
  • Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same
    Patent number: 7253502
    Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: August 7, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Subahu D. Desai, How T. Lin, John M. Lauffer, Voya R. Markovich, David L. Thomas
  • Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same
    Patent number: 7253518
    Abstract: A wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow. A method of making the package is also provided, as is an information handling system (e.g., computer) adapted for utilizing such packages.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: David V. Caletka, Varaprasad V. Calmidi, Sanjeev Sathe
  • Non-flaking capacitor material, capacitive substrate having an internal capacitor therein including said non-flaking capacitor material, and method of making a capacitor member for use in a capacitive substrate
    Publication number: 20070177331
    Abstract: A capacitor material including a thermosetting resin (e.g., epoxy resin), a high molecular mass flexibilizer (e.g., phenoxy resin), and a quantity of nano-particles of a ferroelectric ceramic material (e.g., barium titanate), the capacitor material not including continuous or semi-continuous fibers (e.g., fiberglass) as part thereof. The material is adapted for being positioned in layer form on a first conductor member and heated to a predetermined temperature whereupon the material will not possess any substantial flaking characteristics. A second conductor member may then be positioned on the material to form a capacitor member, which then may be incorporated within a substrate to form a capacitive substrate. Electrical components may be positioned on the substrate and capacitively coupled to the internal capacitor.
    Type: Application
    Filed: April 4, 2007
    Publication date: August 2, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra Das, John Lauffer, Voya Markovich, Kostas Papathomas
  • Method of making circuitized substrate
    Publication number: 20070166944
    Abstract: A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric material to flow into and substantially fill openings in a conductive layer for the bonded structure. Conductive thru-holes are formed within the bonded structure to couple selected ones of the structure's conductive layers. Formation of an electrical assembly is possible by positioning one or more electrical components (e.g., semiconductor chips or chip carriers) on the final structure and electrically coupling these to the structure's external circuitry.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 19, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert Japp, John Lauffer, Voya Markovich, William Wilson
  • Method of making circuitized substrate with split conductive layer and information handling system utilizing same
    Publication number: 20070144772
    Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 28, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: John Lauffer, James Larnerd, Voya Markovich
  • Resistor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said ciruitized substrate, and information handling system utilizing said ciruitized substrate
    Patent number: 7235745
    Abstract: A material for use as part of an internal resistor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. A circuitized substrate adapted for using such a material and resistor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 26, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich
  • Method of improving electrical connections in circuitized substrates
    Publication number: 20070139977
    Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Subahu Desai, John Lauffer, How Lin, Voya Markovich, Ronald Smith
  • Method and apparatus for depositing conductive paste in circuitized substrate openings
    Patent number: 7211470
    Abstract: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 1, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, John M. Lauffer
  • Method of making multilayered printed circuit board with filled conductive holes
    Patent number: 7211289
    Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 1, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James M. Larnerd, John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
  • Method of making a printed circuit board with low cross-talk noise
    Publication number: 20070089290
    Abstract: A method of making a printed circuit board in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.
    Type: Application
    Filed: December 6, 2006
    Publication date: April 26, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: John Lauffer, Voya Markovich, James McNamara, David Thomas
  • Method of making a circuitized substrate having a plurality of solder connection sites thereon
    Publication number: 20070090170
    Abstract: A method of making a circuitized substrate in which solder material (e.g., in paste form) is deposited through a screen onto individual conductors in a spaced pattern of individual solder “islands”. A solder flux is then deposited onto the “islands” causing these to spread out and form a continuous solder layer across the conductor's upper surface. The solder layer is then capable of coupling to an external conductor such as a solder ball, to form an electrical assembly such as might be used within an information handling system such as a personal computer.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Steven Anderson, Scott Moore, Cheryl Palomaki, Son Tran
  • Circuitized substrate with signal wire shielding, electrical assembly utilizing same and method of making
    Patent number: 7209368
    Abstract: A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: April 24, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya Markovich, Corey Seastrand, David L. Thomas
  • Interposer and test assembly for testing electronic devices
    Publication number: 20070075726
    Abstract: A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.
    Type: Application
    Filed: December 4, 2006
    Publication date: April 5, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, Frank Egitto, Voya Markovich
  • Method and apparatus for depositing conductive paste in circuitized substrate openings
    Publication number: 20070048897
    Abstract: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the substrate while substantially simultaneously applying the paste onto the substrate's opposing surface. One example of means for accomplishing such paste application is a squeegee, and in one embodiment, two such squeegees may be used. A porous member is used to engage the substrate's undersurface during the vacuum draw, this member being positioned atop a base vacuum member through which the vacuum is drawn.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 1, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Norman Card, John Lauffer
  • Printed circuit board with low cross-talk noise
    Patent number: 7176383
    Abstract: A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 13, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., David L. Thomas