Abstract: The present disclosure pertains to systems and methods for generating a waterfall display to display a stream of high-speed data measurements. In one embodiment, a system may comprise a communication subsystem to receive a stream of high-speed data measurements. A waterfall generation subsystem may receive the stream of high-speed data measurements from the communication subsystem and identify a plurality of changes in the stream of high-speed data. A subset of data measurements may be selected that includes changes in the high-speed data. The changes may be highlighted through a plurality of modifications. A representation of the subset of data measurements in which changes are highlighted may be generated and presented at a rate below a perception threshold of a human operator. A waterfall display subsystem may generate a human-perceptible waterfall display to represent the stream of high-speed data measurements and the plurality of modifications.

Abstract: A semiconductor device package includes a semiconductor die and an anisotropic thermal conductive structure. The semiconductor die includes a first surface, a second surface opposite to the first surface and edges connecting the first surface to the second surface. The anisotropic thermal conductive structure has different thermal conductivities in different directions. The anisotropic thermal conductive structure includes at least two pairs of film stacks, and each pair of the film stacks comprises a metal film and a nano-structural film alternately stacked. The anisotropic thermal conductive structure comprises a first thermal conductive section disposed on the first surface of the semiconductor die, and the first thermal conductive section is wider than the semiconductor die.

Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.

Abstract: A semiconductor device package includes a first circuit layer and an emitting device. The first circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device is disposed on the second surface of the first circuit layer. The emitting device has a first surface facing the second surface of the first circuit layer, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device has a conductive pattern disposed on the second surface of the emitting device. The lateral surface of the emitting device and the lateral surface of the first circuit layer are discontinuous.

Abstract: A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a third semiconductor die and an external contact. The second semiconductor die is disposed adjacent to the first semiconductor die. The third semiconductor die electrically connects the first semiconductor die and the second semiconductor die. The external contact is electrically connected to the third semiconductor die. An electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die.

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit structure. The circuit structure includes a dielectric layer and a bonding pad. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, where the dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall. The bonding pad is disposed in the recess, where a first pad surface of the bonding pad is adjacent to the first dielectric surface, a second pad surface of the bonding pad is adjacent to the second dielectric surface, and an edge of the bonding pad is spaced from the sidewall of the recess by a first distance.

Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.

Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.

Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.

Abstract: An improved electro hydrodynamic method is provided. The method comprises arranging (11) an electro hydrodynamic device inside an enclosure and distributing (12) positive and/or negative ions inside the enclosure during a charging period with a certain defined amount of power. The distribution of the positive and/or the negative ions inside the enclosure (20) is performed so that a predefined amount of charge is set on the interior of the enclosure (20). Within a predetermined period of time after the charging period has ended, the electrospinning device is activated so as to create a product. Finally, the product is removed from the device. The present invention offers a solution for the problem of non-identical initial process conditions for an electro hydrodynamic process caused by any electric charges on the equipment.

Abstract: An electrospinning device (1; 30) is provided comprising: a container (2) for holding a liquid comprising a polymer melt or a polymer solution; a nozzle (3) arranged to outlet a stream of the liquid from the container; a collecting surface (4) for collecting electro spun material coming from the nozzle during an electrospinning process so as to form a fibrous structure (8) on the collecting surface (4); a voltage supply system (5) arranged to create a voltage difference between the nozzle and the collecting surface (4), one or more electrostatic emitters (10; 38) arranged to locally distribute positive and/or negative ions onto the fibrous structure, and one or more rotatable bodies (6; 36) arranged to cause the collecting surface (4) to face the nozzle (3) and the electrostatic emitters (10; 38) in turn.

Abstract: A fuel cell catalyst for oxygen reduction reactions including Pt—Ni—Cu nanoparticles supported on nitrogen-doped mesoporous carbon (MPC) having enhanced activity and durability, and method of making said catalyst. The catalyst is synthesized by employing a solid state chemistry method, which involves thermally pretreating a N-doped MPC to remove moisture from the surface; impregnation of metal precursors on the N-doped MPC under vacuum condition; and reducing the metal precurors in a stream of CO and H2 gas mixture.

Abstract: A fully variable valve train with a rotary plunger for an internal combustion engine. A motor actuates a high-pressure oil injection pump; when a timing driven electromagnetic valve connected to an oil inlet is opened, high-pressure oil enters a hydraulic cylinder; and when the force applied to a plunger by the hydraulic oil is larger than the force of a valve returning spring, the plunger is pushed to move down, so that a valve is opened. When the valve is required to be return, the timing driven electromagnetic valve connected to the oil inlet is closed, and the timing driven electromagnetic valve connected to the oil inlet is opened; the valve moves up under the action of the valve spring, pushing the plunger to move up and thereby discharging the low-pressure oil out of the hydraulic cylinder, then the plunger and the valve return to the initial positions.

Abstract: An airbag for a vehicle including a main bag body and a tail bag body is provided. The tail bag body extends forward from the main bag body in a vehicle longitudinal direction. The airbag is operable between an undeployed state and a deployed state such that, when the airbag is in the deployed state, the tail bag body extends into a cavity of an instrument panel defined by an upper wall, a front wall, and a lower wall. When in the deployed state, the tail bag body contacts at least one of the upper wall, the front wall, and a lower wall in order to inhibit movement of the main bag body in a vehicle vertical direction.

Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.

Abstract: A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.

Abstract: A package structure includes a substrate, a first electronic component, a second electronic component, a third electronic component and a connection component. The substrate includes a first surface and a second surface opposite the first surface. The first electronic component is disposed at the substrate and has a first active surface exposed from the second surface of the substrate. The second electronic component includes a second active surface facing the first active surface of the first electronic component. The second active surface of the second electronic component is electrically connected to the first active surface of the first electronic component. The third electronic component includes a third active surface facing the first active face of the first electronic component. The connection component electrically connects the third active surface of the third electronic component to the first active surface of the first electronic component. The connection component has at least two bendings.

Abstract: An optical package structure includes a substrate, an emitter, a first detector and a light-absorption material. The substrate has a first surface and a second surface opposite to the first surface, the substrate includes a via defining a third surface extending from the first surface to the second surface. The emitter is disposed on the first surface of the substrate. The first detector is disposed on the first surface and aligned with the via of the substrate. The light-absorption material is disposed on the third surface of the substrate.

Abstract: The present disclosure relates to systems and methods of sag in a power line. In an embodiment, a monitoring device may include a distance sensor and an operating parameter sensor. A processor of the monitoring device may acquire, via the distance sensor, a first distance measurement. The processor may acquire, via the operating parameter sensor, a first operating parameter measurement. The processor may provide an output signal indicating that the power line is sagging when a combination of the first distance measurement and the first operating parameter measurement exceed a first combined distance-operating parameter threshold.

Abstract: A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device.