Abstract: Disclosed are a composite substrate and a method for manufacturing the same, and a semiconductor device structure. In this application, after a buffer layer and an epitaxial growth layer are sequentially formed on a support substrate, the epitaxial growth layer is bonded on a target substrate of which a surface has a bonding layer, and the support substrate and the buffer layer are removed to form the composite substrate at least including the target substrate, the bonding layer and the epitaxial growth layer which are stacked sequentially, the buffer layer has a periodic structure in which a first sublayer and a second sublayer are alternately arranged. In this application, the buffer layer is provided with the periodic structure, so that a stress may be adjusted, and crystal quality of the epitaxial growth layer may be significantly improved.

Abstract: Disclosed are a light-emitting chip, a manufacturing method thereof and an electronic device. The light-emitting chip includes a first substrate; and at least one reflector and a light-emitting pixel layer sequentially located on the first substrate. The light-emitting pixel layer includes at least one light-emitting pixel. The reflector is arranged corresponding to the light-emitting pixel. A first surface, close to the light-emitting pixel, of the reflector is a bowl-shaped surface. The bowl-shaped surface is concave in a direction close to the first substrate. The reflector is configured to reflect light emitted by a corresponding light-emitting pixel and adjust an emission direction and/or an emission angle of the light, so that the light exit rate of the light-emitting chip can be improved, and the light-emitting brightness of the light-emitting chip and electronic device can be further improved.

Abstract: Disclosed are an enhancement-mode switching device and a preparation method therefor. The enhancement-mode switching device includes: a substrate; a channel structure; an n-type semiconductor layer covering a bottom wall of the trench; a p-type semiconductor layer arranged in a gate region; a gate electrode arranged on a side, away from the substrate, of the p-type semiconductor layer; a source electrode arranged in a source region; a drain electrode arranged in a drain region. In the gate region, the p-type semiconductor layer and n-type semiconductor layer are in contact with each other to form a space depletion region in the gate region, and the electronic channel between the source electrode and the drain electrode of the switching device is interrupted, so that the switching device may be effectively turned off under a gate bias voltage of zero, improving control capability of the gate electrode and reliability of the device.

Abstract: Disclosed is an image sensor, comprising: at least one photosensitive unit, where the photosensitive unit includes a main photosensitive region and an auxiliary photosensitive region arranged at the periphery of the main photosensitive region, and a photosensitive component content of the main photosensitive region is different from a photosensitive component content of the auxiliary photosensitive region. The disclosure enlarges a wavelength range of sensible light of each the photosensitive unit by arranging the auxiliary photosensitive region at the periphery of the main photosensitive region of the photosensitive unit, where the photosensitive component content of the main photosensitive region is different from that of the auxiliary photosensitive region. Thereby more image details may be recorded to generate images with high dynamic range, which enables people to experience a visual effect close to a real environment.

Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

Abstract: The present application provides a frontside-illuminated image sensor, including a substrate, a photosensitive unit, and a lens structure. The substrate has a plurality of charge storage regions; The photosensitive unit is above the substrate, and the photosensitive unit includes a plurality of photosensitive sub-units. Each photosensitive sub-unit includes a red photosensitive layer, a green photosensitive layer, and a blue photosensitive layer that are stacked. One photosensitive sub-unit is electrically connected with one charge storage region; the lens structure is on a side of the photosensitive unit away from the substrate.

Abstract: An optical coupling structure includes an alignment layer, a growth substrate and an optical functional layer, the growth substrate being used for epitaxially manufacturing the optical functional layer, and the optical functional layer being aligned with a first through hole in the growth substrate; an optical fiber input end disposed in a second through hole in the alignment layer for improving stability of the optical fiber input end; and an embedding structure used to penetrate through the first and second through holes, which may not only clamp and fix the alignment layer and the growth substrate, effectively improving overall stability of the optical coupling structure, but also align the optical functional layer with the optical fiber input end, and therefore, light emitting from the optical functional layer directly enters the optical fiber input end through the first and second through holes, improving an optical coupling efficiency.

Abstract: This application provides an ultraviolet LED and a manufacturing method thereof. In the manufacturing method, an N-type transition layer is formed above an electron supply layer and/or a P-type transition layer is formed above a hole supply layer, materials of the electron supply layer and the hole supply layer include at least three elements: Al, Ga and N, and materials of the N-type transition layer and the P-type transition layer are GaN; an N electrode is formed on the N-type transition layer, and an ohmic contact is formed between the N-type transition layer and the N electrode; a P electrode is formed on the P-type transition layer, and an ohmic contact is formed between the P-type transition layer and the P electrode.

Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.

Abstract: The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: first forming a first conductive layer on a substrate, where the first conductive layer includes a heavily-doped group III-V compound, then forming an isolation structure on the first conductive layer, then growing a light-emitting structure by using the isolation structure as a mask, where the light-emitting structure includes a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked on the first conductive layer, and a conductivity type of the first semiconductor layer is opposite to a conductivity type of the second semiconductor layer.

Abstract: Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base, wherein the base comprises strip trenches arranged parallelly; and a heterojunction structure located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region and a drain region respectively located at both ends of each of the strip trenches, and a gate region between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.

Abstract: A light-emitting structure includes: a first region and a second region surrounding the first region. The first region includes a plurality of first light-emitting units, and the second region includes a plurality of second light-emitting units. An area of the first light-emitting unit is greater than an area of the second light-emitting unit. The area of the second light-emitting unit in the second region arranged on the edge is relatively small, which improves a doping rate of a light-emitting element in the second region, so that doping rates of the light-emitting element of the light-emitting structure in the first region and the second the area tend to be equal, thereby solving a problem of uneven light-emitting wavelengths in the first region and the second region when the light-emitting unit is prepared by epitaxy.

Abstract: Disclosed are a semiconductor structure and a method for preparing a semiconductor structure, a film bulk acoustic resonator and a method for preparing a film bulk acoustic resonator. The method for preparing a semiconductor structure according to the present application includes: growing a first nitride layer on a surface, including an active silicon layer, of a substrate, and selectively removing a partial area of the active silicon layer to form a hollow structure, so that the first nitride layer and the substrate are partially separated, and then a stress between the substrate and the first nitride layer is released. A crack of the semiconductor structure is reduced and quality of the semiconductor structure is improved while a thickness of the semiconductor structure is guaranteed.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes an N-type semiconductor layer provided on a substrate in a vertical direction, and at least one of multiple-quantum-well structure is formed on the N-type semiconductor layer in a horizontal direction, a P-type semiconductor layer is provided above the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, each multiple-quantum-well structure includes a plurality of semiconductor layers sequentially stacked in the vertical direction and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers, and the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure in the vertical direction. The method is used to manufacture the semiconductor structure.

Abstract: The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

Abstract: A semiconductor structure includes: a substrate, a buffer layer and a multi-channel heterojunction layer which are disposed in a stacking manner, the multi-channel heterojunction layer including a first, a second, . . . , and an n-th heterojunction layers in a direction away from the substrate, where n?2, and each heterojunction layer includes a channel layer and a barrier layer; and an n-type heavily doped layer, which is disposed on a side wall of the multi-channel heterojunction layer, the n-type heavily doped layer being a multi-layer structure. The present disclosure provides the n-type heavily doped layer with the multi-layer structure, which may effectively reduce an ohmic contact resistance of a source region and a drain region.

Abstract: A semiconductor structure includes a substrate, an N+ type gallium nitride epitaxial layer, an N? type gallium nitride epitaxial layer and a first AlGaN layer which are sequentially disposed; a P-type gallium nitride epitaxial layer extending from a surface of a side, away from the substrate, of the first AlGaN layer into the N? type gallium nitride epitaxial layer; and a second AlGaN layer located on a side, away from the substrate, of the first AlGaN layer and the P-type gallium nitride epitaxial layer. According to technical solutions of the present disclosure, an enhancement mode device with a high threshold voltage can be realized and an on-resistance of the device can be reduced.

Abstract: A semiconductor structure includes a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, a source region located at one side of the gate region and a drain region located at another one side of the gate region; and a P-type semiconductor layer, located at least in the gate region and located at a side, away from the substrate, of the barrier layer; where the P-type semiconductor layer includes a non-activated layer, an N-type doped layer and an activated layer which are stacked sequentially, and the non-activated layer is located on a side, close to the substrate, of the P-type semiconductor layer.