Abstract: The present application provides a method of manufacturing a semiconductor structure. The manufacturing method includes following steps: at step S1: forming a first epitaxial structure above a substrate, where the first epitaxial structure is doped with a doping element; at step S2: forming a sacrificial layer above the first epitaxial structure; at step S3: etching the sacrificial layer; at step S4: growing an insertion layer above the first epitaxial structure when the etching of the sacrificial layer is completed; and at step S5: growing a second epitaxial structure above the insertion layer; before proceeding to step S4, repeating step S2 and step S3, until a concentration of the doping element in the first epitaxial structure is lower than a predetermined threshold.

Abstract: The present disclosure provides a semiconductor structure, including: a substrate and a heterojunction structure disposed on the substrate, where the heterojunction structure includes a source region, a drain region, and a gate region disposed between the source region and the drain region, and the drain region is provided with a quantum well structure. The quantum well structure is provided in the drain region of the heterojunction structure, and the quantum well structure is used to generate photons by recombination luminescence, the photons can be radiated not only on the surface region of the potential barrier layer but also into the interior of the heterojunction structure, thereby the release process of electrons captured by the defects can be accelerated to reduce the current collapse effect as well as the dynamic on-resistance.

Abstract: A semiconductor structure and a manufacturing method thereof is provided.

Abstract: The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

Abstract: The present disclosure provides an enhancement-type semiconductor structure and a manufacturing method thereof. The enhancement-type semiconductor structure includes: a semiconductor substrate and a heterojunction structure distributed from bottom to top; where the heterojunction structure includes a channel layer close to the semiconductor substrate and a first potential barrier layer far away from the semiconductor substrate; the heterojunction structure includes a gate region, and a source region and a drain region on two sides of the gate region respectively, and an intermediate layer is sandwiched between the channel layer and the first potential barrier layer in the gate region, the intermediate layer is adapted to depolarize the contacted first potential barrier layer.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located in a source region and a drain region on the etch stop layer. Due to the setting of the etch stop layer, when the P-type semiconductor layer in the gate region is removed by etching, etching can be stopped at the etch stop layer, and the etching depth can be accurately controlled without causing etching damage to the channel layer. The carrier mobility of holes in the channel in the semiconductor structure is improved, and yield and performance of the device are improved.

Abstract: The present disclosure provides a radio frequency device, a silicon carbide homoepitaxial substrate and a manufacturing method thereof. The manufacturing method of the silicon carbide homoepitaxial substrate includes: providing an N-type silicon carbide substrate, forming first grooves in the N-type silicon carbide substrate; forming a defect repair layer on inner walls of the first grooves and outside the first grooves, and forming second grooves in the defect repair layer corresponding to the first grooves; forming an unintentionally doped silicon carbide layer on the defect repair layer, where the second grooves are fully filled with the unintentionally doped silicon carbide layer.

Abstract: The present disclosure provides a light-emitting structure and a manufacturing method thereof. The light-emitting structure includes: a GaN-based LED structure and a nitrogen-containing passivation layer located on a sidewall of the GaN-based LED structure; wherein the GaN-based LED structure includes: a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, conductivity types of the first semiconductor layer and the second semiconductor layer are opposite.

Abstract: Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, and a passivation layer, where the passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate the passivation layer and expose the heterostructure layer; a second semiconductor layer, where the second semiconductor layer is located in the first groove, and the second semiconductor layer does not fully fill the first groove in a horizontal direction; a first electrode, where the first electrode is at least located on a heterostructure layer and the second semiconductor layer that are corresponding to the first groove; and a second electrode located in the second groove.

Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.

Abstract: Disclosed are a semiconductor light-emitting device and a preparation method of the semiconductor light-emitting device. The preparation method of the semiconductor light-emitting device includes: forming a mask layer on a substrate, the mask layer is provided with a plurality of openings exposing the substrate; etching the substrate at each of the plurality of openings to form a first groove, and forming a first reflector in the first groove; epitaxially growing a light-emitting structure on the first reflector, and the light-emitting structure includes a first conductive type semiconductor layer, a multiple quantum well layer and a second conductive type semiconductor layer epitaxial grown in sequence; forming a second reflector in one side of the light-emitting structure away from the first reflector.

Abstract: A semiconductor device includes: a substrate, a first support structure, a first nanowire heterojunction, a source, a drain, and a ring-shaped gate. The substrate includes a first region, and a second region and a third region located on respective sides of the first region; the first support structure is located at least on the second region and the third region; the first nanowire heterojunction includes a first gate section corresponding to the first region, a first source section corresponding to the second region, and a first drain section corresponding to the third region; the first source section and the first drain section are located on the first support structure. The source is located on the first source section, the drain is located on the first drain section, and the ring-shaped gate wraps the first gate section.

Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.

Abstract: Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, a passivation layer, and a cap layer stacked in sequence. The passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate through at least the passivation layer. A first electrode is arranged at least on the cap layer corresponding to the first groove; a second electrode is arranged in the second groove. A Schottky contact is formed between the first electrode and the cap layers, so that a direct contact area between the first electrode and the heterostructure layer may be avoided, a contradiction between the forward turn-on voltage and the reverse leakage of the Schottky diode may be balanced, and a leakage characteristic of the heterostructure layer in a high temperature environment may be suppressed.

Abstract: Disclosed are a semiconductor structure and a manufacturing method therefor, solving a problem that a surface of an epitaxial layer is not easy to flatten as the epitaxial layer has a large stress. The semiconductor structure includes: a substrate; a patterned AlN/AlGaN seed layer on the substrate; and an AlGaN epitaxial layer formed on the patterned AlN/AlGaN seed layer.

Abstract: This application provides an ultraviolet LED and a manufacturing method thereof. In the manufacturing method, an N-type transition layer is formed above an electron supply layer and/or a P-type transition layer is formed above a hole supply layer, materials of the electron supply layer and the hole supply layer include at least three elements: Al, Ga and N, and materials of the N-type transition layer and the P-type transition layer are GaN; an N electrode is formed on the N-type transition layer, and an ohmic contact is formed between the N-type transition layer and the N electrode; a P electrode is formed on the P-type transition layer, and an ohmic contact is formed between the P-type transition layer and the P electrode.

Abstract: The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a gate region, a source region and a drain region; a source region N-type ion heavily-doped layer located in the source region; a drain region N-type ion heavily-doped layer located in the drain region; a gate electrode located in the gate region; a source electrode located on the source region N-type ion heavily-doped layer; and a drain electrode located on the drain region N-type ion heavily-doped layer.

Abstract: The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a channel region, a source region and a drain region; one or more grooves provided in at least one of the source region or the drain region, where, for each of the grooves, a length of a first side edge adjacent to the channel region and located on a bottom wall of the groove is larger than a length of an orthographic projection of the first side edge on a vertical plane in a length direction of the channel region; a source region N-type ion heavily-doped layer and a drain region N-type ion heavily-doped layer; and a gate electrode, a source electrode, and a drain electrode.

Abstract: Disclosed is a full-color LED epitaxial structure, having different area ratios of pillars corresponding to an unit area of a substrate, which is utilized to realize different flow rates of reaction gas around each of the pillars when a light-emitting layer is grown, and different doping efficiency of each element in the growing light-emitting layer, which in turn realizes different composition ratios of each element in the growing light-emitting layer and different light-emitting wavelengths of LED. The above process is simple and the full-color LED semiconductor structure can be produced on a single substrate. And light-emitting wavelengths of LED can be adjusted only by adjusting the area ratio of the pillars to adjust a composition ratio of the light-emitting layer, thus reducing manufacturing processes of the full-color LED.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.