Abstract: The present disclosure provides a light sensing unit, a gallium nitride_(GaN)-based image sensor, and a display apparatus thereof. The light sensing unit includes: red, green, and blue light sensing sub-units, where materials of a red-light sensing layer of each of the light sensing sub-units are GaN-based materials containing indium(In). The materials of the light sensing layers may contain different contents of In, such that the light sensing sub-units are enabled to generate or not generate light sensing electrical signals according to different wave lengths of received light. During a GaN-based material growth process, the contents of In in different regions are controlled to prepare the light sensing sub-units at the same time to increase integration degrees of the light sensing unit, the GaN-based image sensor, and the display apparatus containing the light sensing unit to achieve miniaturization.

Abstract: The present disclosure provides a resonant tunneling diode and a manufacturing method thereof. The resonant tunneling diode includes: a first barrier layer; a second barrier layer; and a potential well layer between the first barrier layer and the second barrier layer, a material of the first barrier layer being AlxInyN1-x-y, 1>x>0, 1>y>0, and/or a material of the second barrier layer being AlmInnN1-m-n, 1>m>0, 1>n>0, and a material of the well layer including a gallium element.

Abstract: Semiconductor structures and manufacturing methods thereof. A semiconductor structure includes: a first epitaxial layer; a bonding layer, on first epitaxial layer and provided with a first through-hole exposing first epitaxial layer; a silicon substrate, on a side of bonding layer away from first epitaxial layer, first epitaxial layer and the silicon substrate being bonded through the bonding layer; a through-silicon-via, in silicon substrate, through-silicon-via communicating with first through-hole; a second epitaxial layer, on first epitaxial layer exposed by first through-hole; a first electrode, on a side of first epitaxial layer away from bonding layer, and electrically coupled with first epitaxial layer; a second electrode, on a side of second epitaxial layer away from first epitaxial layer, and electrically coupled with second epitaxial layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes an N-type semiconductor layer provided on a substrate in a vertical direction, and at least one of multiple-quantum-well structure is formed on the N-type semiconductor layer in a horizontal direction, a P-type semiconductor layer is provided above the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, each multiple-quantum-well structure includes a plurality of semiconductor layers sequentially stacked in the vertical direction and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers, and the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure in the vertical direction. The method is used to manufacture the semiconductor structure.

Abstract: A multi-quantum well structure includes at least one lamination layer, each lamination layer includes a first film layer, an insertion layer and a second film layer, and the at least one lamination layer includes a plurality of lamination layers which are stacked with each other. The insertion layer is located between the first film layer and the second film layer. The insertion layer includes at least one of a monomer structure and a superlattice structure, the first film layer is doped with elements of In, Ga and N, the insertion layer is doped with elements of Al, Ga and N, and the second film layer is doped with elements of Ga and N. The multi-quantum well structure has ability to emit a light with a longer wavelength, and defects and other undesirable phenomena, caused by growing the first film layer with low-temperature epitaxy, may be prevented.

Abstract: Disclosed are a semiconductor light-emitting device and a preparation method for the semiconductor light-emitting device. The semiconductor light-emitting device having a red light sub-pixel region, a green light sub-pixel region, and a blue light sub-pixel region includes a substrate and a blue light epitaxial layer epitaxially grown on the substrate, and a green light epitaxial layer and a red light epitaxial layer continually grown on the green light sub-pixel region and the red light sub-pixel region, respectively, on the blue light epitaxial layer, the green light epitaxial layer and the red light epitaxial layer being distributed on the blue light epitaxial layer at an interval.

Abstract: Disclosed is a graphite disc solving a problem of poor performance uniformity of the epitaxial wafer, which is obtained during material epitaxial growth by using the graphite disc. The graphite disc includes a graphite disc body, where the graphite disc body includes a groove and a plurality of projections on a bottom wall of the groove, and the plurality of projections divide the groove into a plurality of independent regions. According to the graphite disc provided by the present disclosure, a plurality of regions are defined in the groove by using the projections, each region corresponds to one substrate, and different regions are interconnected. Compared with the graphite disc structure with one groove corresponding to one substrate in the related art, a space for gas flow is enlarged, therefore a problem that an edge of the epitaxial wafer is too thick caused by gas flow is alleviated.

Abstract: Disclosed are a quantum well structure and a preparation method therefor, and a light-emitting diode. The quantum well structure includes at least one quantum well and at least one first film layer. The quantum well includes a well layer and a barrier layer alternately stacked, and the well layer includes a first doping element. Each first film layer includes a second doping element. The second doping element is used for adjusting a doping content of the first doping element in the well layer. The first doping element includes at least one of In and Al, and the second doping element includes at least one of Al, Mg, and Si. A content of the first doping element may be adjusted by catalysis of the second doping element, thereby adjusting light-emitting efficiency and a light wavelength of the quantum well as required.

Abstract: The present application provides a method of manufacturing a semiconductor structure. Due to different hole ratios of openings of a mask corresponding to one unit region of a substrate, flow rates of reactive gas in openings are different when growing a light emitting layer. In this way, growth rates of the light emitting layers in openings are different, and doping efficiencies of the light emitting layers in openings are different, such that composition proportions of respective elements in the grown light emitting layer are different, and the light emitting wavelengths of LEDs are different. The processes are simple, and a semiconductor structure applied to a full-color LED can be manufactured on one substrate, which can reduce a size of the full-color LED.

Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present disclosure. The semiconductor structure includes a semiconductor substrate; a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, and each of the isolation structures are located between adjacent stacked structures; each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.

Abstract: A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.

Abstract: Disclosed are a light emitting structure and a preparation method therefor. The method includes: forming a mask layer on a n-type substrate, disposing a plurality of openings in the mask layer; and forming a light emitting unit in each of the plurality of openings, including: forming a metal atomic layer in the opening; forming an n-type semiconductor layer on the metal atomic layer, and forming a light extraction structure on the n-type semiconductor layer; and sequentially forming an active layer and a p-type semiconductor layer on the n-type semiconductor layer and the light extraction structure. In this way, step of peeling off the substrate may be avoided. In addition, with a plurality of discrete light emitting structures formed on the same substrate, a step of cutting a device is avoided, and damage to the device can be prevented.

Abstract: Provided are a bearing system and a power control method for a bearing device. The bearing system comprises a susceptor; a rotating shaft fixed under the susceptor, where the rotating shaft and the susceptor rotate synchronously; a heating wire located under the susceptor, where the heating wire comprises n heating wire units arranged in a circumferential direction of the susceptor, n?2, and temperature of each of the heating wire units is independently controlled; and a power controller configured to: during rotation of the susceptor, control at least one of: a power of a heating wire unit directly under a down end of the susceptor to be less than a power of each of other heating wire units, or a power of a heating wire unit directly under an up end of the susceptor to be greater than a power of each of other heating wire units.

Abstract: Disclosed are a light emitting diode with a vertical structure and a manufacturing method thereof. The manufacturing method includes: forming a metal atom layer on a substrate, the substrate being an n-type substrate; forming an n-type buffer layer on the metal atom layer; forming a light emitting structure on the n-type buffer layer, the light emitting structure including an n-type semiconductor layer, an active layer and a p-type semiconductor layer from bottom to top; disposing a p electrode on the light emitting structure; and disposing an n electrode on one side, away from the metal atom layer, of the substrate. The n-type substrate with conductivity is adopted, and the metal atom layer and the n-type buffer layer are sequentially formed on the n-type substrate, so that conductivity of a device with the vertical structure can be ensured, and stripping and bonding are not needed.

Abstract: Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×1018 cm?3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.

Abstract: Disclosed is a method of manufacturing a semiconductor structure, including: providing a silicon substrate (10), epitaxially growing a functional layer (11) on an upper surface of the silicon substrate, where a material of the functional layer includes a group-III-nitride-based material; implanting ions into an interface between the upper surface of silicon substrate and the functional layer to introduce defects to the interface; or implanting, before epitaxially growing the functional layer, ions to the upper surface of the silicon substrate to introduce defects to the interface.

Abstract: Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base (10), wherein the base (10) comprises strip trenches (101) arranged parallelly; and a heterojunction structure (11) located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region (11a) and a drain region (11b) respectively located at both ends of each of the strip trenches, and a gate region (11c) between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the method, for the substrate, the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer distributed sequentially from bottom to top, the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in first predetermined regions are removed to form grooves. The second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in second predetermined regions and third predetermined regions are retained. Layers retained in second predetermined regions form light emitting units arranged in an array. Various layers retained in third predetermined regions form connection posts, each of which connects adjacent light emitting units.

Abstract: An N-face polar GaN-based device, a composite substrate thereof, and a method of manufacturing the composite substrate are provided in the present disclosure. The N-face polar GaN-based composite substrate includes: a semiconductor substrate, an insulating layer on the semiconductor substrate and a GaN-based material layer on upper surface of the insulating layer; a surface of the GaN-based material layer attached to the insulating layer is Ga-face, and a surface of the GaN-based material layer away from the insulating layer is an N-face. In the present disclosure, the transfer technology is adopted to replace the direct epitaxial growth, which overcomes the difficult growth process, and the N-face polar GaN-based composite substrate with better quality can be obtained.