Abstract: A full digital soft-start circuit adapted for a power supply system is provided. The full digital soft-start circuit includes a ring oscillator, a pulse generator, a counter, and a multiplexer. The ring oscillator generates a plurality of clock signals which are different in phase, while equivalent in duty cycle and frequency. The pulse generator generates a plurality of pulse signals with different duty cycles. The counter generates a multi-bit counting signal. The multiplexer determines whether to transmit the pulse signals generated by the pulse generator so as to generate an output pulse which becomes stable as time going on.

Abstract: A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.

Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.

Abstract: A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror.

Abstract: An image de-interlacing method for estimating an interpolation luminance of an interpolated pixel, including: selecting a plurality of first and second candidate pixels respectively on upper and lower lines adjacent to the interpolated pixel, calculating a plurality of weighted directional differences respectively associated with one of the first candidate pixels and one of the second candidate pixels with weighting values determined by comparing similarity of luminance decreasing/increasing patterns near the associated first and second candidate pixels on the upper and lower lines, selecting a first selected pixel and a second selected pixel respectively from the first and second candidate pixels associated with the smallest weighted directional difference, and obtaining the interpolation luminance according to the first and second selected pixels.

Abstract: A digital-to-analog converter is coupled to a first voltage source and used for converting a digital input into an analog output. The DAC includes a voltage booster providing a first gate-source voltage and a second gate-source voltage to generate a voltage of a first level according to the first voltage source and the first gate-source voltage, and to generate a voltage of a second level according to the voltage of the first level and the second gate-source voltage; and a current-guiding circuit selectively receiving the voltage of the first level or the second level according to the digital input to generate the analog output. The first level and the second level vary with the first voltage source.

Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.

Abstract: A deglitch circuit including signal transmission units is provided. The signal transmission units are connected in serial to form a signal transmission unit string, and a first signal transmission unit of the signal transmission unit string receives a digital signal. Each signal transmission unit includes a first switch, a first delay circuit and a second switch. First and second terminals of the first switch are coupled to a previous signal transmission unit of the signal transmission unit string and an input terminal of the first delay circuit, respectively. The second switch is coupled between an output terminal of the first delay circuit and a first voltage. When the digital signal has a first logic state, the first switch is turned off, and the second switch is turned on. When the digital signal has a second logic state, the first switch is turned on, and the second switch is turned off.

Abstract: A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of cache sets and each of the cache sets includes a plurality of cache lines. The buffer module is coupled to the caches for receiving and storing data evicted due to conflict miss from a source cache line of a source cache set of a source cache among the caches. The migration selector is coupled to the caches and the buffer module. The migration selector selects, from all the cache sets, a destination cache set of a destination cache among the caches according to a predetermined condition and causing the evicted data to be sent from the buffer module to the destination cache set.

Abstract: A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Abstract: Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer.

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency and different phases. The comparing device is coupled to the sampling device, and provides a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value. The output device is coupled to the comparing device, and outputs two of the comparison values in response to edges of the clock signals. The two outputted comparison values serve as a first instruction signal and a second instruction signal respectively. The first and the second instruction signals are referred to in controlling the frequency and the phase of the foregoing clock signals.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.

Abstract: A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Abstract: A differential to single ended converting circuit includes a transconductance circuit having input terminals for receiving differential input voltages and having a first current output terminal for outputting a first current and a second current output terminal for outputting a second current; an offset cancellation circuit having a first controllable current source connected to the first current output terminal and a second controllable current source connected to the second current output terminal; a first transimpedance circuit having an input terminal connected to the first current output terminal and an output terminal for outputting a first voltage; a second transimpedance circuit having an input terminal connected to the second current output terminal and an output terminal for outputting a second voltage; and a first inverter having an input terminal connected to the output terminal of the first transimpedance circuit and an output terminal for outputting a first single ended output voltage.

Abstract: A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.