Patents Assigned to Faraday Technology Corp.
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Patent number: 8068349Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.Type: GrantFiled: April 8, 2008Date of Patent: November 29, 2011Assignee: Faraday Technology Corp.Inventors: Chang-Yu Wu, Ming-Hsin Ku, Shang-Chih Hsieh, Hsin-Shih Wang
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Patent number: 8067965Abstract: A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path.Type: GrantFiled: August 20, 2010Date of Patent: November 29, 2011Assignee: Faraday Technology Corp.Inventors: Cheng-Ta Wei, Ming-Shih Yu
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Patent number: 8054101Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.Type: GrantFiled: May 7, 2009Date of Patent: November 8, 2011Assignee: Faraday Technology Corp.Inventors: Chi-Che Chen, Jung-Chi Ho
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Publication number: 20110231685Abstract: A high speed input/output (HSIO) system and a power saving control method for the HSIO system are provided. The HSIO system has a plurality of transmission speed modes. When an external device is connected to the HSIO system and an auto-configuration link is completed, the power saving control method forcibly sets an interface controller to any desired transmission speed specification in accordance with an actual transmission speed of to-be-transmitted data. Therefore, transmission speed mode of a single physical layer can be changed to achieve a low power transmission.Type: ApplicationFiled: May 20, 2010Publication date: September 22, 2011Applicant: Faraday Technology Corp.Inventors: Po-Yao Huang, Chien-Ting Wang
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Patent number: 8014482Abstract: A signal receiving circuit includes: a sampler, for receiving an analog signal and sampling the analog signal according to a sampling clock to generate a sampling signal; an ADC, coupled to the sampler, for converting the sampling signal to a digital signal; an equalizer, coupled to the ADC, for equalizing the digital signal to generate an equalized digital signal; a quantizer, coupled to the equalizer for quantizing the equalized digital signal to generate a processed digital signal; and a timing recovery circuit, directly connected to the output terminal of the sampler and coupled to the quantizer, for adjusting the timing of the sampling clock according to the processed digital signal and the digital signal. Timing recovery parameter generating circuits are also disclosed.Type: GrantFiled: November 26, 2007Date of Patent: September 6, 2011Assignee: Faraday Technology Corp.Inventor: Kai Huang
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Patent number: 7986290Abstract: Output stage and related method applied to source driver/chip of LCD panel. While performing dot polarization inversion for even/odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even/odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to VDD or VSS so as to turn off the drivers for providing high impedance at the even/odd channels when necessary.Type: GrantFiled: May 21, 2008Date of Patent: July 26, 2011Assignee: Faraday Technology Corp.Inventor: Cheng-Yong Yang
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Publication number: 20110149449Abstract: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: FARADAY TECHNOLOGY CORP.Inventors: Chun-Yu Lin, Ming-Dou Ker, Fu-Yi Tsai
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Patent number: 7965838Abstract: A watermark generating circuit includes: a first computing circuit, for generating a second reference signal according to a computing parameter, an input data and a first reference signal; a second computing circuit, coupled to the first computing circuit, for generating at least one selecting signal to determine an embedding location for a watermark according to the second reference signal; and a register, coupled to the first computing circuit, for registering the second reference signal to transmit the registered second reference signal to the first computing circuit for updating the first reference signal, and for generating the watermark according to the second reference signal.Type: GrantFiled: November 30, 2007Date of Patent: June 21, 2011Assignee: Faraday Technology Corp.Inventors: Yu-Min Wang, Tung-Lung Yu
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Publication number: 20110129014Abstract: A motion detecting method and a motion detector are provided. The motion detecting method includes the following steps. When the type of the current macro block (MB) is intra-type (I-type) or predictively-coded type (P-type), a first procedure or a second procedure is performed. The first procedure includes setting the active flag of the current MB according to the type of the previous MB. The second procedure includes setting the active flag of the current MB according to the motion vectors of the previous MB and the current MB. The present invention is capable of reducing the probability of erroneous motion judgments.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: FARADAY TECHNOLOGY CORP.Inventor: Wan-Ting Lee
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Patent number: 7944194Abstract: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.Type: GrantFiled: December 1, 2008Date of Patent: May 17, 2011Assignee: Faraday Technology Corp.Inventors: Ting-Chun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Patent number: 7945404Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.Type: GrantFiled: April 24, 2008Date of Patent: May 17, 2011Assignee: Faraday Technology Corp.Inventors: Jung-Chi Ho, Sheng-Bin Lin, Yeong-Jar Chang
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Patent number: 7945767Abstract: A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer and the circular instruction buffer. The instruction buffer stores a plurality of instructions, and the circular instruction buffer stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit decodes and pairs the instructions and the recovery instructions. When the branch mis-prediction occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit which is externally connected to the decoding and pairing circuit.Type: GrantFiled: September 30, 2008Date of Patent: May 17, 2011Assignee: Faraday Technology Corp.Inventor: Chih-Yung Chiu
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Patent number: 7912166Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.Type: GrantFiled: October 10, 2007Date of Patent: March 22, 2011Assignee: Faraday Technology Corp.Inventors: Jen-Chien Hsu, Hung-Wen Lu, Chau-Chin Su, Yeong-Jar Chang
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Patent number: 7908530Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.Type: GrantFiled: March 16, 2009Date of Patent: March 15, 2011Assignee: Faraday Technology Corp.Inventor: Cheng-Chien Chen
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Patent number: 7900107Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.Type: GrantFiled: August 20, 2008Date of Patent: March 1, 2011Assignee: Faraday Technology Corp.Inventors: Wang-Chin Chen, Augusli Kifli
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Patent number: 7889541Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.Type: GrantFiled: April 10, 2009Date of Patent: February 15, 2011Assignee: Faraday Technology Corp.Inventors: Wei-Chiang Shih, Chen-Hao Po, Kwo-Jen Liu
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Patent number: 7888970Abstract: A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.Type: GrantFiled: July 29, 2009Date of Patent: February 15, 2011Assignee: Faraday Technology Corp.Inventor: Wang-Chin Chen
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Patent number: 7884617Abstract: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.Type: GrantFiled: December 14, 2008Date of Patent: February 8, 2011Assignee: Faraday Technology Corp.Inventors: Ming-Dou Ker, Po-Yen Chiu, Chun Huang
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Patent number: 7880534Abstract: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.Type: GrantFiled: May 8, 2009Date of Patent: February 1, 2011Assignee: Faraday Technology Corp.Inventors: Din-Jiun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Patent number: 7868668Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.Type: GrantFiled: May 13, 2009Date of Patent: January 11, 2011Assignee: Faraday Technology Corp.Inventors: Yung-Shin Kao, Nan-Chun Lien