Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: Traces routed through a computer depiction of a routing area of a system, such as an electronics system, comprise a plurality of connected nodes. The traces may be smoothed, straightened, or otherwise adjusted (e.g., to correct design rule violations) by assigning forces to the nodes and moving the nodes in accordance with the nodes. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area.

Abstract: A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to be input into the semiconductor and/or response signals generated by the semiconductor device in response to the test signals.

Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics.

Abstract: A method of manufacturing a multilayer printed circuit board (PCB) is provided, the PCB having blind vias connecting to power layers. A portion of the blind vias in the power layers are grouped together to form a cluster of blind vias. Signal layers, provided separate from the power layers, include signal routing channels, with at least some of the signal routing channels aligned above or below the cluster of blind vias of the power layers.

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristic (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart to desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element.

Abstract: An insulative material is applied to one or more selected probe tips to disable those probes, and the probes are brought into contact with a semiconductor die. One or more tests are run on the die to verify sufficient testing of the die without the disabled probes. The process may be repeated with other probes disabled to determine which probes need not be used in testing the die.

Abstract: A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.

Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics.

Abstract: A halide based stress reducing agent is added to the bath of a rhodium plating solution. The stress reducing agent reduces stress in the plated rhodium, increasing the thickness of the rhodium that can be plated without cracking. In addition, the stress reducing agent does not appreciably decrease the wear resistance or hardness of the plated rhodium.

Abstract: An interconnection element and a method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element.

Abstract: An apparatus and method providing improved interconnection elements and tip structures for effecting pressure connections between terminals of electronic components is described. The tip structure of the present invention has a sharpened blade oriented on the upper surface of the tip structure such that the length of the blade is substantially parallel to the direction of horizontal movement of the tip structure as the tip structure deflects across the terminal of an electronic component. In this manner, the sharpened substantially parallel oriented blade slices cleanly through any non-conductive layer(s) on the surface of the terminal and provides a reliable electrical connection between the interconnection element and the terminal of the electrical component.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.

Abstract: Apparatuses and methods for cleaning test probes used in a semiconductor testing machine of the type having a plurality of test probes configured to contact the surface of a semiconductor wafer to test one or more dies formed thereon. In one embodiment, the apparatus includes a roller-support arm and a cylindrical roller supported by the roller-support arm. The roller has an outer surface comprising a sticky material. Debris on the probes will adhere to the sticky material as roller is rolled across tips of the probes. The probes are thereby cleaned.

Abstract: Spring contact elements are attached to terminals of an electronic component, which may be a semiconductor die. The spring contact elements may comprise a flexible precursor element. The precursor element may be over coated with a resilient material. The spring contact elements may be elongate and attached to the terminals at one end. The other end of the spring contacts may be spaced away from the electronic component.

Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.

Abstract: Various structural features for modifying the performance characteristic of cantilevered microelectronic spring structures are disclosed. Generally, the features comprise a protruding member mounted between a supporting substrate and the transverse cantilever beam of a microelectronic spring structure, at a distance spaced apart from the supporting structure from which the beam is cantilevered. The protruding member may be equal to the clearance under the beam, less than the clearance under the beam, or adjustable in height; and may be attached or mounted to either the beam or the substrate. The protruding member may include an adjustable pressure device or an electronic element. The protruding member may induce a reverse wipe.

Abstract: An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.