Abstract: Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.

Abstract: A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads.

Abstract: An image of an array of probes is searched for alignment features. The alignment features are then used to bring contact targets and the probes into contact with one another. The alignment features may be a feature of one or more of the tips of the probes. For example, such a feature may be a corner of one of the tips. An array of probes may be formed to have such alignment features.

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device in a coil pattern over the compliant pad to its end area, forming a helix. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. In an alternative embodiment, the pad is removed to leave a freestanding helical contact.

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device over the compliant pad to its end area. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. A horizontal microelectronic spring contact and method of making the same are also disclosed. The horizontal spring contact has a rigid trace attached at a first end to a terminal of a substrate.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

Abstract: An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.

Abstract: A forming tool with one or more embossing tooth, and preferably, a plurality of such embossing teeth, arranged on a substantially planar substrate, is disclosed. Each embossing tooth is configured for forming a sacrificial layer to provide a contoured surface for forming a microelectronic spring structure. Each embossing tooth has a protruding area corresponding to a base of a microelectronic spring, and a sloped portion corresponding to a beam contour of a microelectronic spring. Numerous methods for making a forming tool are also disclosed. The methods include a material removal method, a molding method, a repetitive-stamping method, tang-bending methods, and segment-assembly methods.

Abstract: A method for replacing a microelectronic spring contact bonded to a terminal of a substrate is disclosed. The method includes removing the microelectronic spring contact from the terminal, such as by cutting the microelectronic spring contact in two adjacent to the terminal. Then, a bonding material, such as a solder paste, is applied to the terminal and a replacement spring contact is positioned on the bonding material. The bonding material is then cured to fix the replacement spring contact in place. The replacement spring contact includes a base configured to fit on or over any protruding material left on the terminal, and at least one resilient cantilever arm extending from the base. In an embodiment of the invention, the base includes at least two legs extending from the base in a direction opposite to the cantilever arm. In an alternative embodiment, the base of the replacement spring contact has a flat bottom, or one or more recesses to receive protrusions on the terminal.

Abstract: Resilient contact structures provide electrical interconnection between a semiconductor die and another electronic component. Multilayered packaging may be formed on the semiconductor die, and the resilient contact structures may be formed on portions of one or more of the layers. Heat dissipating structures may be provided on the die.

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.

Abstract: An interconnection element of a spring (body) including a first resilient element with a first contact region and a second contact region and a first securing region and a second resilient element, with a third contact region and a second securing region. The second resilient element is coupled to the first resilient element through respective securing regions and positioned such that upon sufficient displacement of the first contact region toward the second resilient element, the second contact region will contact the third contact region. The interconnection, in one aspect, is of a size suitable for directly contacting a semiconductor device. A large substrate with a plurality of such interconnection elements can be used as a wafer-level contactor. The interconnection element, in another aspect, is of a size suitable for contacting a packaged semiconductor device, such as in an LGA package.

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.