Abstract: A radio-frequency (RF) transceiver for aligning a time offset (TO) of RF signals transmitted to the RF transceiver by a user equipment (UE) includes first and second processors and first and second system memories. The first processor provides values of a cool-off period, a reset interval, a filter period, a first filter, and a primary threshold to the second processor. The second processor generates a second filter value, first and second threshold values, an instantaneous TO value, and a TO value. The second processor transmits a default TO value and a modified TO value as the TO value to the first processor during first and second time periods, respectively. The first processor generates a control signal based on the TO value. The second processor transmits the modified TO value to the UE based on the control signal.

Abstract: A method for debugging a computer program is proposed. The method includes a step of running at least part of the computer program on a computer, thereby prompting the computer to execute a sequence of instructions and to generate a trace corresponding to the executed sequence of instructions. When the program has generated an exception, selecting a set of one or more exception strings on the basis of the trace, so that each of the exception strings is a unique substring of the trace. The exception strings are indicated to a user or to a debugging tool. The set of exception strings may notably include the ultimate shortest unique substring of the trace. A computer program product is also described.

Abstract: A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.

Abstract: High-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described.

Abstract: A pressure sensor (20) includes a test cell (32) and sense cell (34). The sense cell (34) includes an electrode (42) formed on a substrate (30) and a sense diaphragm (68) spaced apart from the electrode (42) to produce a sense cavity (64). The test cell (32) includes an electrode (40) formed on the substrate (30) and a test diaphragm (70) spaced apart from the electrode (40) to produce a test cavity (66). Both of the cells (32, 34) are sensitive to pressure (36). However, a critical dimension (76) of the sense diaphragm (68) is less than a critical dimension (80) of the test diaphragm (70) so that the test cell (32) has greater sensitivity (142) to pressure (36) than the sense cell (34). Parameters (100) measured at the test cell (32) are utilized to estimate a sensitivity (138) of the sense cell (34).

Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

Abstract: A self-bootstrap driving circuit includes a first input receiving a first control signal; an output, to which a load having an electro-inductive component may be connected; a power switch having first and second current terminals and a control terminal, and being arranged to drive power from a power supply terminal to the load; a bootstrap circuitry arranged to drive the control terminal of the power switch based on the control signal; and a current path between the electro-inductive component of the load and the control terminal of the switch, said current path being arranged to provide direct transfer from said electro-inductive component to said control terminal of the switch of an overvoltage generated at the electro-inductive component to provide an overdrive voltage to said control terminal of the switch.

Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.

Abstract: A system for monitoring and controlling the power of a Radio Frequency (RF) signal in a short-range RF transmitter. An RF signal-generation unit generates the RF signal. A power amplifier amplifies the RF signal. An impedance-matching network matches the output impedance of the power amplifier to input impedance of an antenna. One or more RF power monitors monitor the voltage amplitude of the RF signal at the output of at least one of the RF signal-generation unit, the power amplifier and the impedance-matching network. The one or more RF power monitors further generate at least one alarm signal, based on the voltage amplitude of the RF signal. A control unit modifies at least one operating parameter of at least one of the RF signal-generation unit and the power amplifier, based on the at least one alarm signal generated by the one or more RF power monitors.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state.

Abstract: A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.

Abstract: A processor is configured to execute instructions of a first thread and a second thread. A first return stack corresponds to the first thread, and a second return stack to the second thread. Control circuitry pushes a return address to the first return stack in response to a branch to subroutine instruction in the first thread. If the first return stack is full and borrowing is not enabled by the borrow enable indicator, the control circuitry removes an oldest return address from the first return stack and not store the removed oldest return address in the second return stack. If the first return stack is full and borrowing is enabled by the borrow enable indicator and the second thread is not enabled, the control circuitry removes the oldest return address from the first return stack and push the removed oldest return address onto the second return stack.

Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.

Abstract: A voltage switch for handling negative voltages includes an input terminal coupled to a voltage that is greater than a voltage rating of oxide in the voltage switch, a top capacitor plate pre-charge module including three cascoded p-channel transistors coupled between a supply voltage and a top plate of a capacitor, a bottom capacitor plate pre-charge module including two cascoded n-channel transistors coupled between a bottom plate of the capacitor and ground, and an output voltage module including an output terminal and four cascoded n-channel transistors with control electrodes of a first and fourth of the cascoded n-channel transistors coupled to a boost node. Control electrodes of a second and third of the cascoded n-channel transistors coupled to the top plate of the capacitor. A voltage switch for positive voltages is also disclosed.

Abstract: An interface system has a first media access controller having a first MAC buffer for storing at least one first-type frame in a first frame format according to a first communication protocol. A time synchronization module is arranged to, upon detecting the start of the first-type frame, determine a first timestamp from a master clock signal and latch the first timestamp into a first timestamp register. A processor is arranged to: retrieve the first timestamp from the first timestamp register, and transfer a first-type frame between the first MAC buffer and a first local memory in a block-wise manner as a plurality of blocks. The processor is arranged to process the plurality of blocks of the first-type frame using the first timestamp as retrieved from the first timestamp register.

Abstract: There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack.

Abstract: An integrated circuit comprising voltage modulation circuitry arranged to convert an input voltage level at an input node to an output voltage level at an output node. The voltage modulation circuitry comprises a switching element arranged to connect the input node to the output node when in an ON condition, and switching control module operably coupled to the switching element and arranged to control the connection of the input node to the output node by the switching element in accordance with a switching frequency. The voltage modulation circuitry further comprises frequency control module operably coupled to the switching control module and arranged to receive an indication of the input voltage level at the input node, and to configure the switching frequency based at least partly on the input voltage level indication.