Abstract: An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.

Abstract: A microelectromechanical systems (MEMS) device includes at least two rate sensors (20, 50) suspended above a substrate (30), and configured to oscillate parallel to a surface (40) of the substrate (30). Drive elements (156, 158) in communication with at least one of the rate sensors (20, 50) provide a drive signal (168) exhibiting a drive frequency. One or more coupling spring structures (80, 92, 104, 120) interconnect the rate sensors (20, 50). The coupling spring structures enable oscillation of the rate sensors (20, 50) in a drive direction dictated by the coupling spring structures. The drive direction for the rate sensors (20) is a rotational drive direction (43) associated with a first axis (28), and the drive direction for the rate sensors (50) is a translational drive direction (64) associated with a second axis (24, 26) that is perpendicular to the first axis (28).

Abstract: An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.

Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Abstract: An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. The interconnect structures partially cover the module substrate top surface to define conductor-less areas at the top surface. The amplifier device includes a semiconductor substrate, a transistor, a conductive feature coupled to a bottom surface of the semiconductor substrate and to at least one of the interconnect structures, and a filter circuit electrically coupled to the transistor. The conductive feature only partially covers the semiconductor substrate bottom surface to define a conductor-less region that spans a portion of the bottom surface. The conductor-less region is aligned with at least one of the conductor-less areas at the module substrate top surface. The filter circuit includes a passive component formed over a portion of the semiconductor substrate top surface that is directly opposite the conductor-less region.

Abstract: A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. Each of the messaging queues includes one or more entries for storing data, a set of delegate queue addresses associated with one of the set of messaging queues; and a delegate queue associated with the set of messaging queues. The delegate queue includes a set of entries corresponding to the delegate queue addresses, and each of the entries of the delegate queue indicates whether a corresponding one of the set of messaging queues is storing data.

Abstract: A method for 3D device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal posts. The first die and the second die are stacked such that each metal post extends from a surface of the second die toward a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal posts and the corresponding pads.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

Abstract: A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. The line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages.

Abstract: A system (40) for calibrating an inertial sensor (20) includes a power source (42), a frequency measurement subsystem (44, 48), and a gain determination subsystem (52). A calibration process (110) using the system (40) entails applying (116) a bias voltage (66) to the inertial sensor (20), measuring (114) a drive resonant frequency (46), and measuring (118) a sense resonant frequency (50) of the inertial sensor (20) produced in response to the bias voltage (66). A gain value (32) is determined (124) for calibrating (144) the inertial sensor (20) using a relationship (140) between the sense resonant frequency (50) and the bias voltage (66) without imposing an inertial stimulus on the inertial sensor (20).

Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Abstract: A drive-mode oscillator module generates at least one proof-mass drive signal for use within a micro-electro-mechanical system (MEMS) device. The drive-mode oscillator module comprises at least one gain control component arranged to receive at least one proof-mass motion measurement signal, and to generate a digital modulation control signal based at least partly on the at least one proof-mass motion measurement signal, and at least one modulation component arranged to receive the digital amplitude modulation control signal, and to output at least one proof-mass drive signal. The at least one modulation component is arranged to digitally modulate the at least one proof-mass drive signal based at least partly on the received digital amplitude modulation control signal.

Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.

Abstract: The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

Abstract: A radio frequency power amplifier comprises an input and output terminals, a main and peak amplifier stages, and an output power combiner for combining a main output signal and a peak output signal into an output signal. The output power combiner comprises a first combiner terminal electrically coupled to a main output terminal, a second combiner terminal electrically coupled to a peak output terminal, a first transition structure extending from the first combiner terminal in a first direction to a first end, a second transition structure extending from the second combiner terminal in the first direction to a second end, a first electrical conductor arranged between the first and the second ends, and a second electrical conductor arranged between the second combiner terminal and the output terminal. The first electrical conductor extends in a second direction perpendicular to the first direction. The second electrical conductor extends in the first direction.

Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.

Abstract: A receiver circuit, comprises an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, an input amplification circuit comprising a balanced amplifier input and a balanced amplifier output, a single balanced in-phase mixing circuit comprising a first unbalanced RF mixer input and a balanced in-phase mixing frequency input, and a single balanced quadrature mixing circuit comprising a second unbalanced RF mixer input and a balanced quadrature mixing frequency input. The balanced amplifier input is connected to the balanced balun output, a first terminal of the balanced amplifier output is connected to provide an amplified RF signal to the first unbalanced RF mixer input and a second terminal of the balanced amplifier output is connected to provide a phase-shifted amplified RF signal to the second unbalanced RF mixer input.