Abstract: Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.
Type:
Grant
Filed:
August 9, 2010
Date of Patent:
August 25, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Ravindraraj Ramaraju, Kenneth R. Burch, Charles E. Seaberg
Abstract: A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.
Type:
Grant
Filed:
June 11, 2010
Date of Patent:
August 25, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Michael Priel, Joseph Rabinowicz, Anton Rozen
Abstract: Systems and methods for multi-frame and frame streaming in a Controller Area Network (CAN) with Flexible Data-Rate (FD). In some embodiments, a method may include creating, by a device coupled to a CAN network configured to support a CAN Flexible Data-Rate (FD) protocol, a data frame comprising a field that indicates a multi-frame or streaming transmission, and transmitting the data frame in the multi-frame or streaming transmission. A CAN node may include message processing circuitry configured to receive a data frame comprising a Data Length Code (DLC) field configured to indicate multi-frame operation or streaming operation. The message processing circuitry may be further configured to receive another data frame in the absence of an arbitration process between the data frames.
Type:
Application
Filed:
February 20, 2014
Publication date:
August 20, 2015
Applicant:
Freescale Semiconductor, Inc.
Inventors:
Antonio Mauricio Brochi, Frank Herman Behrens
Abstract: An isolation circuit arranged to provide electrical isolation between at least one control module and at least one driver module. The isolation circuit comprises at least one boost circuit arranged to receive at least one control signal from the at least one control module, and boost the at least one control signal from a first voltage level signal to an increased voltage level signal. The isolation circuit further comprising at least a first capacitive isolation component comprising a first electrically conductive element and at least one further electrically conductive element formed from at least a part of printed circuit board layer, the first and at least one further electrically conductive elements being electrically isolated with respect to one another and arranged to comprise capacitive characteristics there between.
Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.
Type:
Application
Filed:
February 19, 2014
Publication date:
August 20, 2015
Applicant:
Freescale Semiconductor, Inc.
Inventors:
Hussain H. Ladhani, Lu Li, Mahesh K. Shah, Lakshminarayan Viswanathan, Michael E. Watts
Abstract: Various embodiments of semiconductor manufacturing methods include releasing a transparent carrier from a semiconductor wafer assembly that includes a semiconductor wafer in which a plurality of semiconductor devices are formed, an adhesive layer coupled to the semiconductor wafer, a carrier release layer coupled to the adhesive layer, and the transparent carrier coupled to the carrier release layer. The method further includes controlling a laser system to emit a first beam characterized by first laser parameters toward the adhesive layer, where the first laser parameters are selected so that the first beam will compromise a physical integrity of the adhesive layer. The method further includes, after controlling the laser system to emit the first beam toward the adhesive layer, removing the adhesive layer from the semiconductor wafer.
Type:
Grant
Filed:
July 31, 2014
Date of Patent:
August 18, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Kevin P. Ginter, Colby G. Rampley, Jeffrey L. Weibrecht
Abstract: A band-gap voltage reference circuit having first and second branches respectively including first and second groups of transistors of different emitter current conduction areas and current sources for running the first and second groups of transistors at different emitter current densities to generate respective base-emitter voltages, and output terminals connected to receive a regulated voltage (Vout) which is a function of the base-emitter voltages of the first and second groups of transistors. Each of the first and second groups includes at least one npn-type transistor and at least one pnp transistor connected with their emitter-collector paths in series in the respective one of the branches so as to present cumulated base-emitter voltages across the respective group.
Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.
Type:
Grant
Filed:
April 30, 2013
Date of Patent:
August 18, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Cheong Min Hong, Horacio P. Gasquet, Ronald J. Syzdek
Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a first layer of a material that can be used as a gate or a dummy gate. An opening is formed in the first layer in the NVM region. The opening is filled with a charge storage layer and a control gate. A select gate, which may be formed from the first layer or from a metal layer, is formed adjacent to the control gate. If it is a metal from a metal layer, the first layer is used to form a dummy gate. A metal logic gate is formed in the logic region by replacing a dummy gate.
Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.
Abstract: The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link (109) using a single bandwidth DMA (direct memory access) engine (505) and fast Fourier transform/inverse fast Fourier transform processing. (402, 404) The invention exploits fast Fourier transform/inverse fast Fourier transform properties and is particularly suitable for supporting LTE (Long Term Evolution) cellular communication systems (100) The CPRI Media Access Control is configured in each CPRI lane to run at the maximum bandwidth among the bandwidths required. In the uplink, lower bandwidth data samples are padded with zeros and flexible positioning may be used to arrange the data in a CPRI frame. In the downlink, the radio equipment receiver (106) only processes the relevant data and ignores any interpolated samples. The invention is compatible with CPRI and LTE standards.
Type:
Grant
Filed:
November 27, 2013
Date of Patent:
August 18, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Roy Shor, Odi Dahan, Ori Goren, Avraham Horn
Abstract: A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The operands of the first instruction are determined to include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue. The first instruction is stored in a first entry of the second execution queue. A synchronization indicator corresponding to the first instruction in a second entry of the first execution queue is set immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue.
Abstract: A technique for generating a bit log-likelihood ratio (LLR) in a communication system includes generating a demodulated signal based on a received symbol and a reference symbol. An input for a bit LLR generator is generated based on the demodulated signal and a normalization value that is based on the received symbol or the reference symbol. A bit LLR is generated for the received symbol, using the bit LLR generator, based on the input.
Abstract: A method includes forming a packaged integrated circuit that includes forming a lead frame by separating an outer portion of the metal structure into a plurality of leads by stamping. The plurality of leads have sides with a first concavity. The lead frame is further formed by performing an etch on the sides of the plurality of leads to achieve a second concavity on the sides of leads. The second concavity is greater than the first concavity. A semiconductor die is attached to a center portion of the metal structure. Electrical attachments are made between the die and the leads.
Abstract: A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.
Abstract: Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping.
Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.
Abstract: A semiconductor device comprises an integrated circuit including a wire bond pad and a passivation material, and a first gap between a first selected portion of the wire bond pad and the passivation material. The first gap is positioned to contain at least a first portion of a splash of the wire bond pad formed during a wire bond process.
Type:
Grant
Filed:
April 25, 2014
Date of Patent:
August 18, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Tu-Anh N. Tran, David B. Clegg, Sohrab Safai
Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.