Patents Assigned to Freescale Semiconductor
  • Patent number: 9141391
    Abstract: In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thang M. Tran, Trinh Huy Nguyen
  • Patent number: 9142566
    Abstract: A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Asanga H. Perera, Sung-Taeg Kang
  • Patent number: 9141161
    Abstract: A voltage regulation apparatus comprises a plurality of individually switchable current sources coupled to an output for coupling the voltage regulation apparatus to an external load. The output is monitored using a bridge divider and a comparator. The bridge divider generates a feedback voltage, that is compared with a reference voltage, representative of a target voltage to be maintained at the output, when loaded. A digital sequencer unit is coupled to the comparator and responds to the comparator to increase or decrease a number of the plurality of individually switchable current sources activated, thereby causing a collective current generated by the activated number of the plurality of individually switchable current sources to converge on a load current, demanded by the external load.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Eric Rolland
  • Patent number: 9143793
    Abstract: Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erez Steinberg, Moshe Nakash, Yehuda Yitschak
  • Patent number: 9142554
    Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
  • Patent number: 9143115
    Abstract: An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ivan Carlos Ribeiro Nascimento, Andre Luis Vilas Boas
  • Patent number: 9141552
    Abstract: A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrew C. Russell, Ravindraraj Ramaraju
  • Patent number: 9141753
    Abstract: There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Asher Berkovitz, Michael Priel
  • Patent number: 9139155
    Abstract: A diagnostic circuit is provided that includes a FET having a source connected to a first node, a drain, and a gate; a first switch connecting a current-supply node to one of the gate and a second node; a second switch connecting the first node and the second node; a variable current source providing one of a drive current and a test current to the current-supply node; a fire current source configured to provide a fire current to the drain; an error-detecting circuit connected to the second node, a reference terminal, and an error node, the error-detecting circuit generating an error signal to the error node indicating whether an error-detecting parameter at the second node exceeds a reference parameter at the reference terminal; and a control circuit generating control signals to control the variable current source, and the first and second switches.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Randall C. Gray
  • Publication number: 20150263504
    Abstract: A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, John M. Pigott
  • Publication number: 20150260785
    Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Divya Pratap, Sung Jin Jo
  • Patent number: 9134395
    Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Juxiang Ren, Chris C. Dao, Stefano Pietri
  • Patent number: 9136845
    Abstract: A level shifter includes a first branch and a second branch. A trigger of the first branch is coupled to a low voltage input, an inverted high voltage output and a ground. A latch of the first branch is coupled to the inverted high voltage output and a high voltage output. A power gate of the first branch is coupled to an inverted low voltage input, the latch of the first branch and a high voltage supply. A trigger of the second branch is coupled to the inverted low voltage input, the high voltage output and the ground. A latch of the second branch is coupled to the high voltage output and the inverted high voltage output. A power gate of the second branch is coupled to the low voltage input, the latch of the second branch and the high voltage supply.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sayeed Ahmed Badrudduza, Alexander Bernhard Hoefler
  • Patent number: 9135144
    Abstract: A method for identifying a current context during execution of application program code. The method comprises the steps of retrieving static context information for the application program code, identifying at least one active section of the application program code loaded in physical memory; and identifying a current context based at least partly on the at least one identified active section and retrieved static context information.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mihai Matei, Mihail Nistor
  • Patent number: 9136360
    Abstract: Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Ko-Min Chang, Craig T. Swift
  • Patent number: 9135008
    Abstract: A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgeni Ginzburg, Keren Guy, Adi Katz
  • Patent number: 9136804
    Abstract: A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph Staudinger, Paul Hart, Ramanujam Srinidhi Embar, John Vaglica
  • Patent number: 9135129
    Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthew W. Brocker, Steven E. Cornelius, Thomas E. Tkacik
  • Patent number: 9136323
    Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9136327
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo