Abstract: An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.

Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.

Abstract: A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of each task. A random access memory (RAM) is configured to shadow information of the CAM. Transition position storage circuitry is configured to store transition age positions for tasks. Control circuitry is configured to, in response to a command to transition a selected task to a destination scope, access the RAM to determine the current scope for the selected task, use the current scope to perform a match determination with the CAM to determine if any entries corresponding to tasks other than the selected task match the current scope; and for any matching entries, updating a transition age position in the transition position storage circuitry for the corresponding task within the current scope.

Abstract: An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

Abstract: An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.

Abstract: A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations.

Abstract: A BIST circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The BIST circuit includes a finite state machine (FSM), power monitors and a comparator. The FSM sequentially enables at least two power mode states in a predetermined order. In each power mode state, the FSM outputs power mode signals to enable the power supplies used in the corresponding power mode. Each power monitor is connected to a power input node of one of the circuit blocks, and outputs a monitor signal indicative of the voltage at the corresponding power input node when the corresponding power supply is enabled. The comparator compares each monitor signal with a corresponding reference signal and generates a set of power supply status signals.

Abstract: The present application relates to a method and a processing system for automated managing of the usage of alternative code. Code sections including original code and alternative code are retrieved from a code basis and the retrieved code is analyzed to detect an alternative code section. A condition definition associated with the identified alternative code section is further retrieved and the condition of the retrieved condition definition is evaluated. The identified alternative code section is activated in accordance with the evaluation result.

Abstract: A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2).

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.

Abstract: Systems and methods for multi-frame and frame streaming in a Controller Area Network (CAN) with Flexible Data-Rate (FD). In some embodiments, a method may include creating, by a device coupled to a CAN network configured to support a CAN Flexible Data-Rate (FD) protocol, a data frame comprising a field that indicates a multi-frame or streaming transmission, and transmitting the data frame in the multi-frame or streaming transmission. A CAN node may include message processing circuitry configured to receive a data frame comprising a Data Length Code (DLC) field configured to indicate multi-frame operation or streaming operation. The message processing circuitry may be further configured to receive another data frame in the absence of an arbitration process between the data frames.

Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.

Abstract: Systems and methods for adaptive error correction codes (ECCs) for electronic memories. In some embodiments, a memory device, may include a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; and a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory.

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.

Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.

Abstract: The present invention relates to an amplifier circuit, comprising: first to fourth semiconductor amplifiers for controlling first to fourth currents between supply and output terminals, a first input terminal connected to provide a first input signal to a first control terminal of the first semiconductor amplifier and to a fourth control terminal of the fourth semiconductor amplifier, and a second input terminal connected to provide a second input signal to a second control terminal of the second semiconductor amplifier and to a third control terminal of the third semiconductor amplifier. The present invention also relates to a bi-stage amplifier circuit, and to a multi-stage amplifier circuit comprising a cascade of a number of amplifier circuits complying to the present invention, the multi-stage amplifier circuit having a gain control logic prepared to control a gain of at least one of the amplifier circuits.

Abstract: Apparatus (110) for configuring network equipment or devices (101a-101n) during runtime is particularly applicable to network equipment based on QorIQ (trade mark) communication platforms for DPAA (Data Path Acceleration Architecture) optimization purposes and provides a way maintaining an optimal configuration which can change over time acccording to real traffic conditions. The invention may be implemented with any kind of adaptation algorithm for targeting different DPAA features. A flow characteristic function is determined from collected traffic statistics for a multiplicity of traffic flows classified by a common property such as protocol or destination or source. Flow properties are characterised over time, past present and future prediction and in relation to other existing flows based on assigned priorities. A computed flow characteristic function represents the basis for all adaptation algorithms which may be implemented in order to optimise the various DPAA features.

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.