Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

Abstract: An oscillator circuit comprising at least a first component arranged to be statically calibrated to calibrate the oscillator circuit to achieve a symmetrical frequency/temperature profile for the oscillator circuit. The oscillator circuit further comprises at least one further component arranged to be dynamically calibrated to enable an oscillating frequency of the oscillator circuit to be dynamically adjusted, and at least one temperature compensation component arranged to receive at least one temperature indication for the oscillator circuit and to dynamically adjust the at least one further component based at least partly on the at least one received temperature indication. In some examples, the at least one temperature compensation component is arranged to dynamically adjust the at least one further component based on a standardized temperature compensation scheme.

Abstract: There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then add frequency spreading with specific parameters by simulation. The resulting frequency spread signal can be observed. The designer can thus evaluate the reduction in electromagnetic emission level, and repeat this process by iteratively applying frequency spreading each time with specific parameters but without having to modify the schematic of the device and to perform another simulation of the device. The method according to this innovation is extremely rapid as the simulation of the design does not need to be repeated at each run of the frequency spreading simulation.

Abstract: A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.

Abstract: Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Abstract: There is provided a method of estimating a bit error rate in a transport channel of a wireless communication system. The method comprises the receiving a signal from a remote transmitter of the wireless communication system via a physical channel, the signal comprising data and noise forming a plurality of soft bits. The method further comprises the counting, during a period of time, a number of erroneous bits being those soft bits which have an amplitude below ?2A or above +2A with A being the average amplitude of the soft bits received. Next, the number of erroneous bits is divided by a number of total bits received during said period of time in order to obtain the bit error rate. This method provides a way to estimate the BER value without knowing the exact shape of the noise distribution. In an embodiment a selection is made between two estimation algorithms.

Abstract: A gate drive circuit drives a control terminal of a power transistor and comprises: a drive terminal for electrically coupling the control terminal, a first reference source, a first switch arranged between the first reference source and the control terminal, a switch control circuit and a measurement circuit. The first switch is switched-on to turn-off the power transistor. The switch control circuit switches-off the first switch during a transition period to a fully off-state. The measurement circuit outputs a control signal to the switch control circuit in response to a value of a voltage at the control terminal measured when a discharge current flowing to the drive terminal has been reduced to a predetermined threshold, for switching-on the first switch if the measured value is smaller than a threshold voltage.

Abstract: An apparatus for sensing current of a vehicle battery employs an extended counting analog-to-digital conversion process (212) to a chopped and amplified voltage appearing across a low ohmic shunt resistor (203) placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier (209) by matching the gain to the dynamic range of the ADC (212) permits a high dynamic signal sensing.

Abstract: A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

Abstract: Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Abstract: A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

Abstract: A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. The first programmable amplifying current mirror provides in dependence of a control signal ctrl an amplified first current to the common terminal. The second programmable amplifying current mirror conducts away in dependence of the control signal ctrl an amplified second current from the common terminal. The current output circuit provides the output current based on a difference current between the amplified first current and the amplified second current.

Abstract: A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Abstract: A memory system includes a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data. A secondary memory includes a plurality of entries, and each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory. The error correction bits in the secondary memory can be used to correct errors in a subset of the memory having a different number of storage bits than the error correction bits in the memory.

Abstract: A semiconductor device includes, in various embodiments, a memory and a processor, with the processor configured to perform a permission check prior to execution of a memory-access instruction. The permission check comprises evaluating a permission attribute of the memory-access instruction and a permission attribute of a memory location to be accessed. The memory-access instruction is denied unless the permission attribute of the memory-access instruction is compatible with the permission attribute of the memory location to be accessed. In various embodiments, permission attributes are obtained by the processor from a one-time-programmable (OTP) memory module. In various embodiments, the permission attributes are determined based on a source address of the memory-access instruction and an address of the memory location to be accessed. In various embodiments, the OTP memory module stores permission settings that are based on the identity of suppliers for various portions of code stored in the memory.

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.

Abstract: A system for determining a temperature of a first portion of an engine, and related circuit, and related method of operation, are disclosed. In one example embodiment, the system includes a wheel having a plurality of magnetic teeth, and an electrical circuit including a variable reluctance sensor (VRS) including at least one winding, the VRS being positioned proximate the wheel, where the VRS is in thermal contact with the first portion, and a comparator having first and second input terminals and an output terminal, where the comparator is configured to output an output signal at the output terminal. Either the output signal or a further signal generated by the electrical circuit is at least indirectly indicative of a resistance of the at least one winding, whereby an indication of the temperature of the first portion can be determined based upon the output signal or further signal.

Abstract: A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.

Abstract: A real-space charge-transfer device is disclosed. In particular, a Gunn diode is disclosed having a conductive structure fabricated overlying its active region. A secondary signal, other than the normal Gunn diode signal, is generated by the Gunn diode based upon a characteristic of the overlying conductive structure. For example, when the conductive structure is a grate having N teeth the secondary signal will have N secondary oscillation cycles that occur during the duration of a single normal Gunn diode oscillation cycle.