Abstract: Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination.

Abstract: A real-space charge-transfer device is disclosed. In particular, a Gunn diode is disclosed having a conductive structure fabricated overlying its active region. A secondary signal, other than the normal Gunn diode signal, is generated by the Gunn diode based upon a characteristic of the overlying conductive structure. For example, when the conductive structure is a grate having N teeth the secondary signal will have N secondary oscillation cycles that occur during the duration of a single normal Gunn diode oscillation cycle.

Abstract: A method of erasing a plurality of non-volatile memory (NVM) cells on a die includes applying erase signals to the plurality of NVM cells. A subset of the plurality of NVM cells is identified to be soft programmed. Information is identified from a non-volatile storage location that stores a value to identify a particular magnitude from a plurality of possible magnitudes of a starting voltage. A soft program signal is applied to the NVM cells identified for soft programming, wherein the starting voltage of the soft program signal has the particular magnitude.

Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.

Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.

Abstract: Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.

Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.

Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*In(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VTIn(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Abstract: Systems, methods, and circuits for determining one or more switch statuses are disclosed herein. In one example embodiment, such a system for determining a status of a switch having first and second terminals includes a first port configured to be coupled to the first terminal, a second port configured to be coupled to the second terminal, and a capacitor coupled between the first port and ground. Additionally, the system includes a comparator device having first and second input ports and an output port, the first input post being coupled at least indirectly to the first port, a current source coupled to the first input port, and a voltage source coupled between the second port and the second input port. The comparator device is configured to provide an output signal at the output port that is at least sometimes indicative of the status of the switch.

Abstract: A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.

Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.

Abstract: A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.

Abstract: A method of decoding a received SC-FDMA symbol in a receiver in a OFDM communication system is described. The method comprises calculating an approximate constellation energy {circumflex over (K)} from channel matrices Hi for all subcarriers i, a noise covariance matrix S, and a data signal power matrix C associated with the OFDM symbol, an approximate constellation energy {circumflex over (K)}. The approximate constellation energy {circumflex over (K)} is calculated according to: Q i = H i H ? S - 1 ? H i ; Q ^ = 1 N sc ? ? i = 0 N sc - 1 ? Q i ; K ^ = diag ? ( ( Q ^ + C - 1 ) - 1 ? Q ^ ) The method further comprises decoding the received symbol using at least the associated approximate constellation energy {circumflex over (K)}. Also, a receiver, an apparatus, an OFDM communication system and a computer program product for such decoding are described.

Abstract: An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

Abstract: A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.