Abstract: A content addressable memory (CAM) and methods of operating a CAM are provided. The method for operating a CAM includes: during a first mode, performing a search function in a CAM bit array, the search result output at a match port of the CAM bit array; and during a second mode, columnwise reading data in the CAM bit array, the read column data output at the match data port of the CAM bit array. The method may include writing the CAM bit array with a predetermined data pattern. The method may further include providing an indication of pass/fail based upon comparing the read column data with expected data.

Abstract: A method includes, in one implementation, receiving a first set of instructions of a first thread, receiving a second set of instructions of a second thread, and allocating queues to the instructions from the first and second sets. During a time when the first and second threads are simultaneously being processed, changeable number of queues can be allocated to the first thread based on factors such as the first and/or second thread's requirements or priorities, while maintaining a minimum specified number of queues that are allocated to the first and/or second thread. When needed, one thread may be stalled so that at least the minimum number of queues remains reserved for another thread while attempting to satisfy thread-priority requests or queue-requirement requests.

Abstract: An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. The signal line may extend parallel to the surface. The coupling line may extend parallel to the signal line and may be arranged between the surface and the signal line.

Abstract: Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.

Abstract: A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.

Abstract: A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Abstract: A transceiver circuit for operating in a controller area network (CAN), having a CAN bus network and a control unit, that supports a flexible data rate (CAN FD), is described. The transceiver circuit comprises: a transmit CAN path and a receive CAN path; an input node on the transmit CAN path; a detection module operably coupled to the input node on the transmit CAN path and arranged to receive an input frame from the control unit before the input frame is transmitted on the CAN bus network and determine whether the input frame on the transmit CAN path comprises a CAN FD frame; and at least one switching module, operably coupled to the detection module and coupleable to the CAN bus network, where the at least one switching module is operable to impart a first voltage value on the CAN bus network in response to the input frame being determined as comprising a CAN FD frame.

Abstract: A phased-array receiver comprises a plurality of analog beamforming receive channels, each comprising an antenna element arranged to receive a radio frequency signal and a channel output arranged to provide an analog channel output signal. At least one of the plurality of analog beamforming receive channels comprises an in-phase downconversion mixing circuit connected to the antenna element and a local oscillator source and arranged to provide a downconverted in-phase signal to a phase rotation circuit, and a quadrature downconversion mixing circuit connected to the antenna element and the local oscillator source and arranged to provide a downconverted quadrature signal to the phase rotation circuit. The phase rotation circuit is arranged to provide to the channel output a phase-shifted analog output signal generated from the downconverted in-phase signal and the downconverted quadrature signal.

Abstract: A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref.

Abstract: A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the main software program is suspended by the CPU due to the execution of a subroutine; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the ongoing subroutine, from accessing a hardware-protected region of the stack, comprising at least one stack frame associated with a return address from which the main software program resumes execution after termination of the execution of the subroutine. A processor, a method and a computer program are also claimed.

Abstract: An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain, and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.

Abstract: A switching power converter for DC-DC converting has an inductance coupled between a power output and a high side switch in a controller device. The controller device has an error amplifier coupled to the power output and a reference voltage for activating the high side switch. The controller device has a bypass circuit including a bypass switch coupled between the supply input and the power output, a bypass driver having a first input coupled to the power output and a second input coupled to the reference voltage, and an output coupled to the bypass switch for activating the bypass switch. The controller further has a high bypass current sensor for generating a transient signal based on a current via the bypass switch, and a bandwidth control circuit for increasing the bandwidth of the error amplifier based on the transient signal.

Abstract: A method of performing register allocation for at least one program code module. The method comprises constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colourable. The method further comprises, if it is determined that the constructed restriction graph is not colourable, determining whether at least one alternative form of the at least one program instruction is available, and modifying the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.

Abstract: An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit.

Abstract: A charging circuit for at least one bootstrap charge storage element within an inertial load driver circuit is described, the at least one bootstrap charge storage element comprising a first node operably coupled to an output node of at least one switching element of the inertial load driver circuit.

Abstract: A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.

Abstract: A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.

Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

Abstract: The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits N and a first particular bit rate RN corresponding to digital signals occurring after the digital decimation filter. A digital sigma-delta modulator converts the first digital test signal into a second digital test signal having a second particular number of bits M<N thereby corresponding to a digital signal occurring at an input of the digital decimation filter. A DAC converts the second digital test signal into an analog signal, and a filter to filter the analog signal to obtain an analog test signal for testing the analog portion.

Abstract: A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells.