Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.

Abstract: MEMS devices (100) and methods for forming the devices have now been provided. In one exemplary embodiment, the MEMS device (100) comprises a substrate (106) having a surface, an electrode (128) having a first portion coupled to the substrate surface, and a second portion movably suspended above the substrate surface, and a stress-release mechanism (204) disposed on the electrode second portion, the stress-release mechanism (204) including a first slot (208) integrally formed in the electrode. In another exemplary embodiment, the substrate (106) includes an anchor (134, 136) and the stress-release mechanism 222 is formed adjacent the anchor (134, 136).

Abstract: Automatic gain control is provided in a sigma-delta analog-to-digital converter. The automatic gain control is entirely or partly provided by an amplifier and an attenuator within the sigma-delta analog-to-digital converter. The amplifier within the sigma-delta time continuous loop prior to quantization and an attenuator in the feedback prior to summation with incoming signals. Scaling within the sigma-delta analog-to-digital converter results in lower current requirements for automatic gain control without disturbing or minimizing disturbance of the stability of a sigma-delta topology. By providing at least part of the automatic gain within the analog-to-digital converter, the specifications or requirements of the LNA or baseband amplifiers may be reduced or limited.

Abstract: An integrated circuit, wafer, and method for manufacturing an integrated circuit that inhibits the analysis of the circuit via reverse engineering. An integrated circuit includes a target circuit and a reverse engineering prevention circuit. The reverse engineering prevention circuit includes a decryption circuit, a nonvolatile memory, and an automatic read/enable signal generation circuit. When provided with a decoding enable signal and decoding data, the decryption circuit decodes data to perform authentication. When the authentication is successful, the decryption circuit outputs a memory enable signal. When provided with the memory enable signal, the nonvolatile memory enables the writing of data. The automatic read/enable signal generation circuit acquires the data written to the nonvolatile memory to generate a circuit enable signal, which is provided to the target circuit to activate the target circuit.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A method for removing direct current (DC) interference from a signal received by a communication receiver is provided that removes both a DC offset signal induced by the communication receiver and transmitter. The method includes removing the estimated DC offset from the received signal, correcting a frequency shift in the received signal, estimating a second DC offset signal induced by a source of the received signal, such as a transmitter and removing the estimated second DC offset from the received signal. The receiver DC offset signal is estimated and removed prior to performing a timing carrier offset correction using Barker code manipulation to remove receiver-induced DC offset interference and to sum all Barker chips after effectively multiplying Barker codes to correlate to a Barker sequence unaffected by the receiver DC offset signal.

Abstract: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Abstract: A computer model simulation for an MRAM cell. In one example, the MRAM cell includes a magnetic tunnel junctions (MTJ) with multiple free magnetic layers. In one embodiment, the simulation implements a state machine whose states variables transition based on indications of magnetic fields passing thresholds. In one embodiment, the conductance values utilized from the model are derived from measured data that is curve fitted to obtain first and second order polynomial coefficient parameters to be used in the model.

Abstract: According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, forming an inductor on the semiconductor substrate, forming an etch hole in at least one of the etch stop layer and the semiconductor substrate to expose the substrate between the first and second trenches, isotropically etching the substrate between the first and second trenches through the etch hole to create a cavity within the substrate, and forming a sealing layer over the etch hole to seal the cavity.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: Device characterization performed with a test system including a fixture and multiple frequency dependent test boards. In one embodiment, testing is performed with multiple sets of input and output test boards wherein each set is frequency dependent at different frequencies. In some examples, the test board includes an impedance transformer that is a quarter wave length of the fundamental frequency (f0) of a frequency of which the board is dependent. In some examples, S-parameters and load pull measurements are obtained for the device under test with the test boards at different frequencies.

Abstract: The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.

Abstract: A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.

Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Abstract: An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit device further includes a memory component. The memory component includes an input to receive the latched first predecode value and the latched second predecode value, a first bit line, and a plurality of word lines coupled to the first bit line. Each word line is associated with a corresponding bit of the latched second predecode value. The integrated circuit device further includes logic having an input to receive the corresponding bit of the latched first predecode value. The logic is to precharge the first bit line directly responsive to only a value at the corresponding bit of the latched first predecode value.

Abstract: A video encoder including a processing block and an external memory storing a current frame and a reference frame. The processing block includes a memory interface, a local memory and a processor. The processor encodes the current frame in raster scan macroblock order for FMO using information from the reference frame, converts encoded information into compressed information, and organizes the compressed information according to a predetermined FMO. The processor organizes the compressed information according to any suitable FMO organization such as scattered, interleaved, etc. The processor stores the compressed information into multiple slice groups into the local memory or into the external memory, where the slice groups are organized according to the FMO. The processor loads a search window macroblock into the local memory if not already stored in the local memory. The processor may generate unfiltered reconstructed information and store the unfiltered reconstructed information into the local memory.

Abstract: A flowmeter is provided that comprises a leadframe assembly (140) and a body (144) disposed at least partially around the leadframe assembly (140). The body (144) has a flow passage therethrough that comprises a first channel (178) having a first port (166), a second channel (180) having a second port (168), and a flow altering element (182) disposed within the second channel (180). First and second pressure sensors (174 and 176) are disposed within the body (144) and coupled to the leadframe assembly (140) for measuring a first pressure within the first channel (178) and a second pressure within the second channel (180), respectively. An integrated circuit (155), which is coupled to the leadframe assembly (140), to the first pressure sensor (174), and to the second pressure sensor (176), is configured to determine the rate of flow through the flow passage from the first pressure and the second pressure.

Abstract: Amplitude level control circuit for an oscillator comprising first means arranged to generate a first current for driving the oscillator; and second means arranged to generate a second current such that in direct current conditions the second current is arranged to be a predetermined ratio of the first current, wherein the second current is arranged to be added to a reference current to form a feedback current such that in direct current conditions the first current is determined by the reference current, the ratio of the feedback current and first current and the ratio of the first current and second current, wherein the second means is further arranged to reduce the second current as oscillations of the oscillator increase, thereby reducing the first current.

Abstract: An improved method of bonding an insulated wire (14) that has one end connected to a first bond pad (16) to a second bond pad (18) includes moving a tip of a capillary (20) holding the bond wire (14) over the surface of the second bond pad (18) such that the bond wire (14) is rubbed between the capillary tip (20) and the second bond pad (18), which tears the bond wire insulation so that at least a portion of a metal core of the wire (14) contacts the second bond pad (18). The wire (14) is then bonded to the second pad (18) using thermocompression bonding. The tip of the capillary (20) is roughened to enhance the tearing of the bond wire insulation.

Abstract: A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.