Abstract: In an active region, a first parallel pn layer in which first first-conductivity-type regions and first second-conductivity-type regions are disposed to repeatedly alternate with one another is provided while in a termination region, a second parallel pn layer in which second first-conductivity-type regions and second second-conductivity-type regions are disposed to repeatedly alternate with one another, a first semiconductor region of the second conductivity type and configuring a voltage withstanding structure, and a second semiconductor region of the second conductivity type are provided. An impurity concentration of each of the plurality of first first-conductivity-type regions and the plurality of second first-conductivity-type regions is reduced in proportion to an impurity concentration of a region directly thereabove. The region directly thereabove is the first semiconductor region or the second semiconductor region.

Abstract: A semiconductor module includes: a semiconductor chip including a main electrode; a connection conductor electrically connected to the main electrode; a housing portion surrounding the semiconductor chip and at least a part of the connection conductor; a sealing material filled in a space surrounded by the housing portion; and a connection unit fixed to the housing portion. The conductive portion, which is a part of the connection conductor, is exposed from a surface of the sealing material. The connection unit includes: a connection terminal joined to the conductive portion of the connection conductor; and a support that is formed separately from the housing portion and supports the connection terminal.

Abstract: A permanent field magnet is disposed between two armatures parallel to each other, and includes a first field magnet section facing a first armature of the two armatures, and a second field magnet section facing a second armature of the two armatures that is different from the first armature. The first field magnet section includes a first main magnet that generates a magnetic field for the first armature and a first auxiliary magnet that increases magnetic flux of a magnetic pole of the first main magnet. The second field magnet section includes a second main magnet that generates a magnetic field for the second armature and a second auxiliary magnet that increases magnetic flux of a magnetic pole of the second main magnet. The first main magnet and the second main magnet, or the first auxiliary magnet and the second auxiliary magnet, are permanent magnets magnetized in the same direction.

Abstract: A comparator circuit configured to output an output voltage at a first logic level, upon an input voltage exceeding a first threshold voltage, and output the output voltage at a second logic level, upon the input voltage dropping below a second threshold voltage lower than the first threshold voltage. The comparator circuit includes a converter circuit configured to convert the input voltage of the comparator circuit into a first voltage and a second voltage lower than the first voltage, and a logic circuit configured to output a voltage, as the output voltage of the comparator circuit, that is at the first logic level, upon the first voltage exceeding a third threshold voltage, and at the second logic level, upon the second voltage dropping below a fourth threshold voltage lower than the third threshold voltage.

Abstract: In an active region, a first parallel pn layer is provided in which a plurality of first first-conductivity-type regions and a plurality of first second-conductivity-type regions are disposed so as to repeatedly alternate with one another; in a termination region, a second parallel pn layer is provided in which a plurality of second first-conductivity-type regions and a plurality of second second-conductivity-type regions are disposed so as to repeatedly alternate one another; in the termination region, a first semiconductor region of a second conductivity type, is selectively provided between a first main surface of a semiconductor substrate and the second parallel pn layer, the first semiconductor region configuring a voltage withstanding structure and surrounding a periphery of the active region. An other second-conductivity-type region between the first semiconductor region and the plurality of second second-conductivity-type regions in a thickness direction is provided and has a thickness of 0.

Abstract: An armature includes a plurality of cores arranged in a straight line and discontinuous with each other, a plurality of coils wound around each of the cores, and a holding section configured to hold the cores. At least one of the cores include division cores separate from each other and arranged in an axial direction thereof. Each of the division cores has a flange at a contact surface thereof that is in contact with the holding section, and at least a portion of the contact surface protrudes toward the holding section to form the flange.

Abstract: Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.

Abstract: A first conductive pattern includes a first input region overlapping a first semiconductor device and a second input region overlapping a second semiconductor device. An output electrode of the first semiconductor device and an output electrode of the second semiconductor device are connected with each other by a first wiring member. The output electrode of the second semiconductor device and a second conductive pattern are connected with each other by a second wiring member. A ratio of a current flowing from the second input region to the second conductive pattern via the second semiconductor device, relative to a current flowing from the first input region to the second conductive pattern via the first semiconductor device, is equal to or greater than 0.90 and equal to or less than 1.10.

Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a sintered metal such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

Abstract: A method of manufacturing a semiconductor device, includes; preparing an insulated circuit substrate including a circuit layer having a main surface and a side surface inclined to a normal direction of the main surface; irradiating the side surface of the circuit layer with a laser beam so as to roughen at least a part of the side surface of the circuit layer and provide an oxide film on the roughened side surface of the circuit layer; and bonding a semiconductor chip to the main surface of the circuit layer via a solder layer.

Abstract: A conductive member constituting a wiring structure includes a first bonding section bonded to an electronic component, a second bonding section bonded to a connection target for the electronic component, and a raised section that protrudes upward from the first bonding section and is connected to the second bonding section. The conductive member has a wire member passage through which a wire member passes, and which is provided in at least a part of the raised section. The wire member passage enables the wire member to be disposed along the raised section from the first bonding section to the second bonding section such that the wire member intersects a surface of the raised section.

Abstract: A superjunction semiconductor device has: a semiconductor substrate of a first conductivity type; a buffer layer of the first conductivity type, provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate; a drift layer of the first conductivity type, provided on the buffer layer and having an impurity concentration lower than that of the buffer layer; and a parallel pn structure having first column regions of the first conductivity type and second column regions of a second conductivity type repeatedly alternating one another in a direction parallel to the front surface. A subset of the first and second column regions are located in a termination structure portion and have depths that become shallower stepwise towards an end of the semiconductor substrate, where the second column regions are provided with bottoms thereof in the drift layer.

Abstract: There is provided a drive circuit of a switching element and an intelligent power module both capable of preventing deterioration of a switching loss of the switching element. A gate drive circuit includes a first current supply section which supplies a first current to a gate terminal provided in an IGBT when a gate voltage of the gate terminal is lower than a first voltage, a second current supply section which supplies a second current smaller than the first current to the gate terminal when the gate voltage of the gate terminal is higher than a second voltage which is the same as or higher than the first voltage, and a third current supply section which supplies a third current smaller than the first current and larger than the second current to the gate terminal when the gate voltage of the gate terminal is lower than a third voltage lower than the first voltage.

Abstract: A semiconductor device, including first and second conductive patterns, a plurality of first semiconductor chips each having a switching device, a plurality of second semiconductor chips each having a diode device, a plurality of first wires, respectively coupling low-potential electrodes of the switching devices and the second conductive pattern, and a plurality of second wires, respectively coupling anode electrodes of the diode devices and the second conductive pattern. Lengths of the first and second wires are substantially equal. The first semiconductor chips and the second semiconductor chips are arranged on the first conductive pattern in two rows, each row being in a first direction and including at least one first semiconductor chip and at least one second semiconductor chip, the first direction being parallel to a predetermined side of the first conductive pattern. The first and second wires are each in a second direction orthogonal to the first direction.

Abstract: A switching control circuit for a power supply circuit that includes an inductor configured to receive a rectified voltage corresponding to an alternating current (AC) voltage, and a transistor configured to control a current flowing through the inductor, the power supply circuit generating an output voltage from the AC voltage, the switching control circuit being configured to switch the transistor. The switching control circuit comprises: a signal output circuit configured to output a signal to turn on the transistor, after lapse of a first time period since the inductor current reaches a first predetermined value after the transistor is turned off, the first time period corresponding to a conduction period during which a parasitic diode of the transistor conducts; and a driver circuit configured to turn on the transistor based on the signal, and turn off the transistor, based on a feedback voltage corresponding to the output voltage.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided via a gate insulating film, second semiconductor regions of the second conductivity type underlying the trenches, third semiconductor regions of the second conductivity type between adjacent trenches, a first electrode, and a second electrode. The silicon carbide semiconductor device has an active region end portion, which is free of the first semiconductor regions, and in which the third semiconductor regions are apart from sidewalls of the trenches and are connected to the second semiconductor regions.

Abstract: A switching control circuit for a power supply circuit that generates an output voltage from an AC voltage. The power supply circuit includes a rectifier circuit rectifying the AC voltage, an inductor receiving the rectified AC voltage, and a transistor controlling an inductor current flowing through the inductor. The switching control circuit controls switching of the transistor, based on the inductor current and the output voltage. The switching control circuit includes a target value output circuit that outputs a target value of a peak value of the inductor current for shaping a waveform of the peak value so as to be similar to a waveform of the rectified voltage, and a drive signal output circuit that outputs a drive signal to turn on the transistor upon the inductor current falling below a predetermined value and turn off the transistor upon the peak value of the inductor current reaching the target value.

Abstract: A power supply circuit that generates an output voltage from an AC voltage inputted thereto. The power supply circuit includes a rectifier circuit rectifying the AC voltage, an inductor receiving a rectified voltage from the rectifier circuit, a transistor controlling an inductor current flowing through the inductor, and an integrated circuit switching the transistor based on the inductor current and the output voltage. The integrated circuit includes a sample-and-hold circuit that samples-and-holds a voltage corresponding to the rectified voltage in a predetermined timing, an output circuit that outputs a limit voltage based on the voltage held by the sample-and-hold circuit, indicating a limit value for limiting the inductor current, and a signal output circuit that receives the limit voltage and a voltage corresponding to the inductor current, to thereby output a signal to turn off the transistor upon determining that a current value of the inductor current exceeds the limit value.

Abstract: A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.

Abstract: A semiconductor module includes: a wiring board including a ceramic substrate and conductor patterns on a first surface of the ceramic substrate; a semiconductor element arranged on at least one of the conductor patterns on the first surface of the ceramic substrate; a sealing insulator that seals the wiring board and the semiconductor element; and an insulating member disposed on the first surface of the ceramic substrate in a gap between the conductor patterns that are adjacent to each other, the insulating member extending in an extending direction of the gap and dividing an area in the gap where the sealing insulator fills the gap so that the insulating member is separate from respective edges of the conductor patterns adjacent to each other.