Abstract: A short circuit detector is included in a power converter, the power converter being configured to supply power to a load via a first arm including a first semiconductor switch and a second arm including a second semiconductor switch. The short circuit detector includes a Rogowski coil; and a detection circuit configured to detect a short circuit in one of the first arm, the second arm and the load, based on a detection signal obtained from the Rogowski coil. The Rogowski coil is inserted into both: (i) first current path through which a first current flows in common with the first arm and the load, and (ii) a second current path through which a second current flows in common with the second arm and the load.

Abstract: To provide a nitride semiconductor device excellent in switching characteristics. A nitride semiconductor device includes: a gallium nitride layer having a first principal surface and a second principal surface located on an opposite side to the first principal surface and having a trench formed from the first principal surface to the second principal surface side; and a field effect transistor formed in the gallium nitride layer, wherein the trench has a first side surface and a second side surface inside the trench, the first side surface is a nitrogen face in the surface layer of which nitrogen atoms are located, the second side surface is a gallium face in the surface layer of which gallium atoms are located, and the field effect transistor has: a gate insulating film formed on the first side surface; and a gate electrode formed in the trench and covering the gate insulating film.

Abstract: An integrated circuit for a power supply circuit that includes a state-indicating circuit, which is a first or second circuit when the power supply circuit is of a non-isolated or isolated type, as the case may be. The integrated circuit including a voltage generation circuit that generates, at a first terminal, a voltage that is (1) lower than a first level, when the first circuit is coupled to the first terminal, (2) higher than a second level, when the second circuit is coupled to the first terminal, and (3) higher than the first level and lower than the second level, when no state-indicating circuit is coupled to the first terminal, and a determination circuit that determines that the power supply circuit is of the non-isolated or isolated type, when the voltage at the first terminal is lower or higher than the second level, as the case may be.

Abstract: A terminal structure includes a pair of plate sections including first and second plate sections respectively provided spaced apart from each other in a thickness direction of the nut, a connection plate section extending in the thickness direction of the nut and connects respective one ends of the pair of plate sections to each other, a terminal section protruding from the other end of the first plate section of the pair of plate sections and faces the connection plate section, and a holding section provided at at least one of the connection plate section or the terminal section, and restricting rotation of the nut and movement of the nut in a direction intersecting the thickness direction. The pair of plate sections, the connection plate section, the terminal section, and the holding section are constituted by one plate-shaped body.

Abstract: A semiconductor device encompasses a mounting member having a copper-based wiring layer; first covering layer which contains nickel, covering the wiring layer so that a part of upper surface of the wiring layer is exposed in opening; joint layer metallurgically joined to the wiring layer in the opening; second covering layer which contains nickel, metallurgically joined to the joint layer on upper surface of the joint layer; semiconductor chip having bottom surface covered with the second covering layer. The joint layer has lower layer in contact with the wiring layer, upper layer in contact with the second covering layer, and intermediate layer between the lower layer and the upper layer, the lower layer and the upper layer have intermetallic compounds as main components which contain tin, copper and nickel, and the intermediate layer is alloy containing tin as the main component and no lead.

Abstract: A nitride semiconductor device including: a gallium nitride substrate; and a vertical MOSFET provided on the gallium nitride substrate, the vertical MOSFET including: an N-type drift region provided in the gallium nitride substrate; a P-type well region provided in the drift region; an N-type source region provided in the well region; a gate insulating film provided on a surface of the well region; and a gate electrode provided on the surface of the well region via the gate insulating film, wherein the well region includes a first well region and a second well region higher in acceptor element concentration than the first well region, the second well region being located between the first well region and the gate insulating film and being in contact with the source region.

Abstract: An active region has, in a periphery thereof, a p-type outer peripheral region that has sequentially from a front surface of a semiconductor substrate, a p++-type contact extension portion, a p-type base extension portion, and an upper portion and a lower portion of a p+-type extension portion, so as to form, at an outer end portion thereof, steps that are recessed stepwise toward a center of the active region and that in a depth direction, are arranged in ascending order of proximity thereof to the center. An innermost JTE region configuring a voltage withstanding structure contacts an outer end portion of the contact extension portion. Beneath the JTE region, a p+-type embedded region is provided at a same depth as the lower portion of the extension portion so as to be apart from the JTE region and the outer peripheral region and surround the periphery of the active region.

Abstract: A semiconductor device having, in an outer peripheral portion of an active region, and in a depth direction from a front surface of a semiconductor substrate, first to fourth outer peripheral regions, to thereby form steps that are recessed stepwise toward the center of the semiconductor device by a same width, and are arranged in an ascending order of the proximity to the center in the depth direction. The first, second, and fourth outer peripheral regions, respectively, are formed concurrently with p++-type contact regions, a p-type base region, and lower portions of p+-type regions in a center portion of the active region. An impurity concentration of the third outer peripheral region is 0.1 times to 0.5 times the impurity concentration of the upper portions of the p+-type regions. A voltage withstanding structure is formed in contact with an outer end of the first outer peripheral region.

Abstract: A gate drive circuit 22A, in order to cause an IGBT 211a in a semiconductor elements 21u to switch to the ON state according to the signal level of an input signal SinUH, includes a constant current supply unit 223uA configured to supply constant current to the gate G of the IGBT 211a, a switching signal input terminal Tsw4 to which a switching signal Ssw4 is input, a signal level determination unit 226uA configured to determine a signal level of the switching signal Ssw4, and a drive capability switching unit 224uA configured to, by changing a current amount of constant current output from the constant current supply unit 223uA, based on a determination result in the signal level determination unit 226uA and a signal level of the input signal SinUL, switch the drive capability of the constant current supply unit 223uA.

Abstract: A nitride semiconductor device includes a GaN-based semiconductor layer; and an insulating film provided on a first surface of the GaN-based semiconductor layer, the insulating film containing O atoms, and other constituent atoms other than O. An interface between the GaN-based semiconductor layer and the insulating film has a terminating species which terminates a dangling bond of a Ga atom, the terminating species has an outermost electron shell in which one electron is deficient from an allowed number of outermost electrons, and is an atom or molecule having stronger bond to the Ga atom than a H atom, an amount of Ga—O bonds is greater than an amount of bonds between the Ga atoms and the other constituent atoms.

Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.

Abstract: Provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; a current sensing portion for detecting current flowing through the transistor portion; an emitter electrode set to an emitter potential of the transistor portion; a sense electrode electrically connected to the current sensing portion; and a Zener diode electrically connected between the emitter electrode and the sense electrode. Provided is a semiconductor device fabricating method including providing a transistor portion in a semiconductor substrate; providing a current sensing portion for detecting current flowing through the transistor portion; providing an emitter electrode set to an emitter potential of the transistor portion; providing a sense electrode electrically connected to the current sensing portion; and providing a Zener diode electrically connected between the emitter electrode and the sense electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film provided on one surface of the semiconductor substrate; a first resistance layer including polysilicon provided on the first insulating film; a second insulating film provided on the first resistance layer; a second resistance layer including polysilicon provided on the second insulating film so as to overlap with the first resistance layer; a third insulating film provided on the second resistance layer; a first electrode provided over the third insulating film and electrically connected to the second resistance layer; and a second electrode electrically connected to the first resistance layer, wherein the first resistance layer and the second resistance layer each include a body part and a first contact part having a higher impurity concentration than the body part, and the respective first contact parts are in contact with each other.

Abstract: A semiconductor device having a semiconductor chip and a control circuit. The semiconductor chip has a gate electrode pad connected to the gate of an output element and the gate of a current monitor element, a sense emitter electrode pad connected to the sense emitter of the current monitor element and to the anode of the temperature detection diode via a current limiting element, and a cathode electrode pad that is connected to the cathode of the temperature detection diode, the cathode being grounded without being connected to the emitter of the output element. In a temperature detection mode, the control circuit receives a temperature detection voltage via the sense emitter electrode pad and detects the temperature state of the output element. In a current detection mode, the control circuit receives a sense current via the sense emitter electrode pad and detects the current state of the output element.

Abstract: The present invention is directed to provide a semiconductor device capable of protecting a switching element even though having a capacitor connected to a control signal input terminal of the switching element. Semiconductor device includes an IGBT including a gate configured to be input a gate signal and a current detection terminal used to detect at least one of overcurrent or short-circuit current, a gate capacitor arranged between the gate and a reference potential terminal, the gate capacitor being disconnected from the gate as needed, and a disconnection unit configured to disconnect a connection between the gate capacitor and the gate when a detection current being a current output from the current detection terminal is equal to or larger than a first current set on a basis of a minimum current causing oscillation in a loop circuit formed by including the IGBT and the gate capacitor.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.

Abstract: A semiconductor module, including a cooler having first and second flow passages respectively formed on first and second sides of the semiconductor module that are opposite to each other, and a third flow passage connecting the first and second flow passages. The semiconductor module further includes a laminated substrate disposed on the cooler and having first to third circuit boards, a first sensing chip having a sensing function for detecting a temperature and a first non-sensing chip not having the sensing function, disposed on the first circuit board side by side along the third flow passage, and a second sensing chip having the sensing function and a second non-sensing chip not having the sensing function, disposed on the third circuit board side by side along the third flow passage. The first and second sensing chips are respectively disposed on the second side and the first side of the semiconductor module.

Abstract: Provided is a semiconductor device including a semiconductor substrate; a hydrogen donor that is provide inside the semiconductor substrate in a depth direction, has a doping concentration that is higher than a doping concentration of a dopant of the semiconductor substrate, has a doping concentration distribution peak at a first position that is a predetermined distance in the depth direction of the semiconductor substrate away from one main surface of the semiconductor substrate, and has a tail of the doping concentration distribution where the doping concentration is lower than at the peak, farther on the one main surface side than where the first position is located; and a crystalline defect region having a crystalline defect density center peak at a position shallower than the first position, in the depth direction of the semiconductor substrate.

Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.

Abstract: A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 ?m from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×1013/cm3. In the deep region of the first-conductivity-type semiconductor layer, a maximum value of a concentration of boron is less than 1.0×1014/cm3.