Abstract: A semiconductor device includes a main element and a sensing element each including a drift region of a first conductivity-type, a well region of a second conductivity-type provided at an upper part of the drift region, a first main electrode region of the first conductivity-type provided at an upper part of the well region, a gate electrode buried with a gate insulating film interposed in a trench, and a main electrode connected to the first main electrode region, the isolation region including an element-isolation insulating film provided on a top surface of a semiconductor base body interposed between the well regions, and a first wire provided on a top surface of the element-isolation insulating film and electrically connected to the main electrode of the main element.

Abstract: A semiconductor module includes a mounting substrate, a transistor mounted on the mounting substrate, a housing configured to house a semiconductor element, a first sealing layer filled in a space inside the housing to seal the transistor, a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer, and a wire electrically connected to the transistor, in which the wire includes a first portion covered with the first sealing layer and a second portion covered with the second sealing layer.

Abstract: A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.

Abstract: A wire protecting part partially encloses a first lead frame and a second lead frame and has an enclosing surface from which the first and second lead frames protrude. The enclosing surface is parallel to semiconductor chips, and includes a water stop part protruding, from the enclosing surface, between the first and second lead frames.

Abstract: A semiconductor device includes a first insulated circuit board that is rectangular with first to fourth sides, including a first input wiring board and a first output wiring board each extending in a first direction parallel to the first side and being adjacent to each other. The first output wiring board includes a first output region electrically connected to a first output terminal and a first connection wiring region electrically connected to the output electrodes of the plurality of first semiconductor chips and being closer to the second side than is the first output region. The first connection wiring region has a first slit extending in the first direction from an end of the first connection wiring region at a side thereof where the first output region is located.

Abstract: A semiconductor device includes a first semiconductor module and a second semiconductor module that are connected in parallel between the positive terminal and the negative terminal of a direct-current power source. The first semiconductor module includes a first input terminal electrically connected to the positive terminal, a second input terminal electrically connected to the negative terminal, a first housing, and a first wiring bar that is provided in the first housing and is electrically connected to the first input terminal. The second semiconductor module includes a third input terminal electrically connected to the positive terminal, a fourth input terminal electrically connected to the negative terminal, a second housing, and a second wiring bar that is provided in the second housing, is electrically connected to the fourth input terminal, and is magnetically coupled to the first wiring bar.

Abstract: A semiconductor device including: an output element connected to a load and configured to perform switching to operate the load; a drive circuit configured to output a drive signal to thereby cause the output element to perform the switching; an external terminal configured to be connected to a constant current source that is external to the semiconductor device, and to receive a constant current from the constant current source; a temperature sensor connected to the external terminal, and configured to operate with the constant current, detect a temperature of the output element, and output a temperature detection value; a temperature state detection circuit configured to output a temperature state of the output element, based on a result of comparing the temperature detection value with a reference threshold; and an abnormal level notification circuit configured to send out a notification upon determining that the temperature state is at an abnormal level.

Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

Abstract: An integrated circuit for a power supply circuit that generates an output voltage from an alternating current (AC) voltage, the power supply circuit including a transistor configured to control a current flowing through an inductor. The integrated circuit comprises: a first terminal, to which a first capacitor is coupled, that receives a voltage corresponding to the AC voltage; a driver circuit turns on the transistor in response to a predetermined condition being satisfied, and turns off the transistor based on a feedback voltage corresponding to the output voltage and the voltage corresponding to the AC voltage, an ON period of the transistor inversely correlating to a level of the voltage corresponding to the AC voltage; and a discharge circuit that discharges the first capacitor in a time period from a first timing at which the transistor is turned off to a second timing at which the transistor is turned on.

Abstract: A semiconductor device, including a cooling body, a semiconductor unit including a wiring portion electrically connected to a semiconductor chip, and a sealing member sealing the entire semiconductor unit over a cooling surface of the cooling body. The sealing member includes a first portion and a second portion which surrounds the first portion in a plan view. The first portion seals a central portion of a main electrode of the semiconductor chip, and has a first sealing surface opposite the cooling surface of the cooling body. The second portion seals a wiring portion to thereby surround the first portion in the plan view, and has a second sealing surface opposite the cooling surface. A distance in a thickness direction of the semiconductor device from the cooling surface to the first sealing surface, is smaller than a distance in the thickness direction from the cooling surface to the second sealing surface.

Abstract: A semiconductor module includes a laminate substrate including an insulating plate and first and second circuit boards on an upper surface of the insulating plate, the first semiconductor device on an upper surface of the first circuit board, a first main terminal, and a first metal wiring board that electrically connects the first semiconductor device to the first main terminal. The first metal wiring board has a first bonding section bonded to an upper surface electrode of the first semiconductor device, a second bonding section bonded to an upper surface of the second circuit board, a first coupling section that couples the first bonding section to the second bonding section, a first raised section that rises upward from an end portion of the second bonding section. The first raised section has an upper end that is electrically connected to the first main terminal.

Abstract: A semiconductor apparatus includes: a base, an insulating substrate arranged on the base, a semiconductor element arranged on the insulating substrate, a case joined to the base and housing the semiconductor element, and a sealing material supplied in the case. The case includes a terminal block that extends in a first direction from an inner wall surface of the case. The terminal block is arranged thereon a terminal that is electrically connected to the semiconductor element via a wiring member. The terminal block includes a projecting portion that extends, in plan view, in the first direction from a first position of a distal end portion of the terminal to a second position. A first distance between the first position and the second position is at least 1 mm.

Abstract: Provided is a semiconductor device including a bonding layer made from sintered material and having a configuration capable of avoiding a variation in life span. The semiconductor device includes a conductive plate having a main surface, a semiconductor chip deposited to be opposed to the main surface of the conductive plate, and a bonding layer including porous sintered material and arranged between the conductive plate and the semiconductor chip, wherein a first outer edge of a bonding interface between the bonding layer and the conductive plate is located on the inside of an outer circumference of the semiconductor chip and is located on the inside of a second outer edge of a bonding interface between the bonding layer and the semiconductor chip.

Abstract: A semiconductor device, including: a semiconductor element configured to generate an output current that varies with a change in a temperature of the semiconductor element; a temperature detection circuit that detects the temperature and outputs a temperature detection signal based on the detected temperature; and a correction circuit that causes the output current of the semiconductor element to change based on the temperature detection signal.

Abstract: A semiconductor device includes: a baseplate; an insulating substrate on the baseplate; a semiconductor element on the insulating substrate; a case bonded to the baseplate by an adhesive, the case surrounding a space in which the semiconductor element is positioned; and an encapsulating material filling the space surrounded by the case, in which, the case includes a claw, the claw includes: a protrusion protruding from an inner wall surface of the case; and a hook inclined from the protrusion, a space being sandwiched between the hook and the inner wall surface of the case.

Abstract: An integrated circuit for a semiconductor device that includes a first terminal for receiving a power supply voltage, a second terminal to which a load is to be coupled, and first and second metal-oxide-semiconductor (MOS) transistors each having a drain electrode and a source electrode, the source electrodes being respectively coupled to the first and second terminals. The integrated circuit includes a first line coupled to the drain electrode of the first MOS transistor and the drain electrode of the second MOS transistor, a second line to which a first voltage lower than the power supply voltage is applied, a first device configured to couple the first line and the second line, to prevent the first line from being brought into a floating state, and a detection circuit configured to detect a first abnormality in at least the first MOS transistor based on a voltage level of the first line.

Abstract: A first gate wiring layer is a 2-layered structure in which a polysilicon wiring layer and a metal wiring layer containing aluminum are sequentially stacked. The polysilicon wiring layer and the metal wiring layer surround a periphery of an active region. In a portion of a periphery of the first gate wiring layer, the polysilicon wiring layer and the metal wiring layer contact each other via a contact hole of an interlayer insulating film and in remaining portions thereof, are electrically insulated from each other by the interlayer insulating film. The first gate wiring layer, in portion separate from a gate pad, is configured having relatively more of the metal wiring layer with a resistance value lower than that of the polysilicon wiring layer. The resistance value of the first gate wiring layer is adjusted to be relatively high in a portion near the gate pad, as compared to the portion separate from the gate pad.

Abstract: An impurity region of P-type that the field effect transistor of the nitride semiconductor device includes has a peak position at which concentration of P-type impurities reaches a maximum at a position located away from an interface with a gate insulating film. The impurity region has an inflection point at which concentration of the P-type impurities changes from increase to decrease toward the interface or a rate of decrease in the concentration of the P-type impurities increases toward the interface at a position located between the interface and the peak position.

Abstract: A silicon carbide semiconductor device includes a parallel pn layer that includes a standard portion and first and second portions. The standard portion is located at a center of the parallel pn layer in a depth direction and charge balanced. The first and second portions are respectively located closer to the first and second main surfaces than is the standard portion. In the first portion, an amount of a second-conductivity-type charge is greater than that of the first-conductivity-type regions, and continuously increases with a first gradient in a first direction from the standard portion toward the first main surface. In the second portion, an amount of charge of the first-conductivity-type regions is greater than that of the second-conductivity-type regions, and the amount of charge of the second-conductivity-type regions continuously decreases with a second gradient in a second direction from the standard portion toward the second main surface.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type1, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate insulating films, gate electrodes, a first electrode, and a second electrode. The second semiconductor layer has a second semiconductor region of a second conductivity type, an impurity concentration of the second semiconductor region increases in the depth direction, has a maximum value at a predetermined depth, and from the predetermined depth, in the depth direction, decreases; a half-width of the impurity concentration is 0.15 ?m or less; and an impurity concentration of the plurality of first semiconductor regions is constant in the depth direction.