Abstract: A semiconductor device includes a first semiconductor unit that includes a first substrate including a first wiring board to which a first semiconductor chip is bonded, a second semiconductor unit that includes a second substrate including a second wiring board to which a second semiconductor chip is bonded, a cooling unit including a first cooling surface and a second cooling surface that are opposite to each other and respectively have the first semiconductor unit facing the first substrate thereon and the second semiconductor unit facing the second substrate thereon, and an output terminal provided at a first side of the cooling unit and being connected to both the first wiring board and the second wiring board.

Abstract: A semiconductor apparatus includes a semiconductor module, a substrate having a control unit that controls an operation of the semiconductor module, a busbar that allows a current to flow through the semiconductor module, and a shield arranged between at least respective opposing surfaces of the control unit and the busbar that oppose to each other.

Abstract: A source pad of a main semiconductor element is electrically connected to an n+-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

Abstract: A switching control circuit controls switching of a switching device, which controls a resonance current of a resonant converter, with a frequency corresponding to an output voltage of the resonant converter. The switching control circuit includes a detection circuit configured to detect a difference between a first timing at which the switching device is turned on and a second timing at which a polarity of the resonance current reverses, and a signal output circuit configured to output a driving signal with a preset minimum frequency, responsive to the difference becoming so small as to satisfy a predetermined condition.

Abstract: A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.

Abstract: An object of the present invention is to provide a semiconductor device capable of suppressing loss in a switching element at high temperature without increasing radiation noise of the switching element. A semiconductor device includes an IGBT including a gate to which a gate signal is input, a temperature detection element that detects temperature of the IGBT, and a capacitance adjustment unit that is arranged between the gate of the IGBT and a reference potential terminal and that adjusts a capacitance between the gate and an emitter of the IGBT according to a detection temperature detected by the temperature detection element.

Abstract: Between the front surface of a semiconductor substrate and an n?-type drift region, a p++-type contact region, a p-type base region, a p+-type high-concentration region, and an n-type current spreading region are provided directly beneath a gate pad, sequentially from a front side of the semiconductor substrate so as to face an entire surface of a gate pad, via a field oxide film. The high-concentration region is electrically connected to source electrode wiring via a p++-type wiring region. N+-type regions that are electrically floating (or n+-type wiring regions of the source potential) are selectively provided between the front surface of the semiconductor substrate and the contact region. The n+-type regions have a function of drawing out holes in the high-concentration region and discharging the holes to the source electrode, when the voltage applied to the drain electrode rapidly increases with respect to the potential of the source electrode.

Abstract: A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, and contains nickel or copper, an entire back surface of the bonding layer being electrically connected to and in direct contact with an electrode in the semiconductor device; an anti-oxidation layer disposed on the bonding layer; and a protective layer disposed directly on a top surface of a peripheral portion of the bonding layer on which the anti-oxidation layer is absent, covering an outer peripheral edge of the bonding layer, wherein the protective layer is made of an electrically insulating resin.

Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

Abstract: A neutron detector having high sensitivity of detection for low energy neutrons is provided. The neutron detector 10 includes a detecting element including a Si semiconductor layer 2, a first electrode 1 formed on one main surface of the Si semiconductor layer 2 and a second electrode 4 formed on the other main surface of the Si semiconductor layer 2, in which the Si semiconductor layer 2 includes a P-type impurity region 2a in contact with the second electrode 4 and an N-type impurity region 2b in contact with the first electrode 1; and a radiator 8 arranged to face the first electrode 1. In addition, a personal dosemeter and a neutron fluence monitor including the same are provided.

Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Abstract: Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.

Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.

Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.

Abstract: A power conversion device includes a sealing material that fills the housing space of a case and that has a sealing surface located above a peak point of a wire included in a semiconductor unit in a side view of the device. The power conversion device further includes a buffering member that extends in a predetermined direction in plan view of the device and that has a buffering bottom surface located above the peak point of the wire and under the sealing surface in the side view.

Abstract: A semiconductor device includes an insulated circuit substrate, a semiconductor chip, a printed circuit board, an interposer, and a sealing member, the interposer including a plurality of post electrodes each having one end bonded to the semiconductor chip via a solder layer, an insulating layer provided to be separately opposed to the semiconductor chip and provided with a first penetration hole filled with part of the solder layer, and a conductor layer provided to be opposed to the printed circuit board and connected to another end of each of the post electrodes via the insulating layer.

Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.

Abstract: A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.

Abstract: IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.

Abstract: A semiconductor module includes: a first die pad having a first face, and a second face directed in a direction opposite to the first face, a first outer lead positioned in the direction in which the second face is directed relative to the first die pad, a first inner lead connecting the first die pad and the first outer lead to each other and having a stepped portion, a first semiconductor chip joined to the second face, and a sealing material sealing the first die pad and the first semiconductor chip, in which the sealing material includes a first sealing portion joined to the first face and constituted of a first resin composition, and a second sealing portion joined to the second face and constituted of a second resin composition lower in thermal conductivity than the first resin composition, and the first sealing portion has an exposed face constituting a part of an outer surface of the sealing material, a first joining face joined to the first die pad, and a second joining face joined to the stepped por