Patents Assigned to Fujitsu Microelectronics Limited
  • Publication number: 20110148495
    Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Taiki UEMURA, Yoshiharu TOSAKA
  • Patent number: 7906840
    Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 15, 2011
    Assignees: Kyocera Corporation, Oki Electric Industry Co., Ltd., Kabushiki Kaisha Toshiba, Fuji Xerox Co., Ltd., Fujitsu Microelectronics Limited, Renesas Technology Corp., Ibiden Co., Ltd., Kanji Otsuka, Yutaka Akiyama
    Inventors: Kanji Otsuka, Yutaka Akiyama
  • Patent number: 7872612
    Abstract: An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 18, 2011
    Assignees: Renesas Electronics Corporation, Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, Fuji Xerox Co., Ltd., Ibiden Co., Ltd, Kyocera Corporation
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Chihiro Ueda
  • Publication number: 20100316003
    Abstract: According to one embodiment, a method for wireless communication includes performing a first scan of a plurality of wireless channels of a wireless communication network by simultaneously utilizing at least two radios of a base station. The method also includes determining a channel quality metric for at least two of the wireless channels in response to the first scan. The method further includes selecting a first wireless channel of the plurality of wireless channels in response to determining the channel quality metrics. In addition, the method includes communicating on the first wireless channel utilizing the at least two radios of the base station.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Aram Sukiasyan, Claude E. Bedard
  • Patent number: 7844934
    Abstract: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 30, 2010
    Assignees: Renesas Electronics Corporation, Panasonic Corporation, Fujitsu Microelectronics Limited, Kabushiki Kaisha Toshiba
    Inventors: Yusaku Ono, Osamu Suga, Kazuyuki Sakata, Hirofumi Taguchi, Yushi Okuno, Toshiaki Sugioka, Daisuke Kondo
  • Publication number: 20100258926
    Abstract: A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED (Formerly Fujitsu Microelectronics Limited)
    Inventors: Takao Nishimura, Kouichi Nakamura
  • Publication number: 20100246079
    Abstract: A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.
    Type: Application
    Filed: February 17, 2010
    Publication date: September 30, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventor: Teruo SUZUKI
  • Publication number: 20100235686
    Abstract: An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 16, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Shuhei SATO, Takashi Sato
  • Publication number: 20100229134
    Abstract: A layout verification method for verifying a layout of a semiconductor device by a computer having a memory storing layout data and information of operation conditions for a plurality of operation modes in which the semiconductor device is expected to assume during its testing and practical use, the semiconductor device including a semiconductor substrate of one conductivity type, a plurality of wells accommodating at least one of the circuit elements and being applicable to a plurality of different bias voltages in dependence of the operation modes, the method includes specifying combination of all the adjacent pairs of the wells located adjacently to each other within the semiconductor substrate, and the distance of each of all the adjacent pairs of the wells in reference to the layout data, determining, for each of the wells.
    Type: Application
    Filed: February 4, 2010
    Publication date: September 9, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Yutaka MIZUNO, Tomoyuki Yamada
  • Patent number: 7791852
    Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: September 7, 2010
    Assignees: Fujitsu Microelectronics Limited, OKI Semiconductor Co., Ltd., Kyocera Corporation, Kabushiki Kaisha Toshiba, Fuji Xerox Co., Ltd., Renesas Technology Corp
    Inventors: Kanji Otsuka, Tamotsu Usami, Yutaka Akiyama, Tsuneo Ito, Yuko Tanba
  • Patent number: 7772628
    Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Wensheng Wang
  • Publication number: 20100197251
    Abstract: According to one embodiment, a power combiner configured to receive at least two input signals and combine the input signals to generate an output signal. The power combiner may include at least two input layers and an output layer located between the input layers. Each layer may be in the shape of a slotted loop.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 5, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventor: Chee Hong Lai
  • Patent number: 7765510
    Abstract: A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtaining an optimum solution of a route even if the via is changed to the redundant via.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 27, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Ikuo Ohtsuka
  • Patent number: 7760567
    Abstract: A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies a voltage difference of a node pair after the operation start of the word line driving circuit. A switch circuit is provided between the bit line pair and the node pair. The switch circuit has coupled the access side of the bit line pair to an access side of the node pair at an instant of the operation start of the word line driving circuit, and has separated a non-access side of the bit line pair from a non-access side of the node pair at an instant of operation start of the sense amplifier.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 20, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Hiroyuki Kobayashi
  • Patent number: 7760125
    Abstract: An A/D conversion circuit including a plurality of resistor elements connected in series between a low-potential power supply and a high-potential power supply. The A/D conversion circuit includes a plurality of comparators that compare a reference voltage divided by each of the resistor elements with an analog input voltage, the comparators having a sample-and-hold function for holding a sampled analog input voltage. The plurality of comparators also include a high-order bit comparator and a low-order bit comparator having different sampling sources. The high-order bit comparator may be configured to compare the analog input voltage and one of the reference voltages to obtain a determination result. The low-order bit comparator may old the analog voltage from the time that the low-order bit comparator retrieves the analog input voltage until the low-order bit comparator performs comparison.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yoshiaki Shimizu, Hisao Suzuki, Kenji Ito, Masashi Kijima
  • Publication number: 20100180053
    Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Koji Takenouchi, Seiji Suetake
  • Patent number: 7754619
    Abstract: A method of forming a liquid coating on a substrate that reduces the amount of consumption of the coating liquid and achieves a more even distribution of the thickness of the liquid coating film. The method may include supplying a solvent to a surface of a substrate, starting a supply of a coating liquid to the surface of the substrate while rotating the substrate at a first rotation speed, stopping a rotation of the substrate by decelerating the rotation of the substrate at a deceleration larger than 30000 rpm/sec at a point of time when the supply of the coating liquid is stopped, and then rotating the substrate at a second rotation speed. Accordingly, the dispense amount of the coating liquid is reduced and the film thickness of the coating liquid is flatten.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomoaki Muramatsu, Yuko Kaimoto, Ichiro Omata
  • Patent number: 7755125
    Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Wensheng Wang
  • Publication number: 20100172267
    Abstract: A method for cooperative data transfer includes establishing a primary wireless connection with a primary access station. The primary wireless connection uses a primary synchronization channel that is transmitted during a first frame of a super frame. The super frame comprises a plurality of frames. The method also includes detecting a secondary synchronization channel generated by an alternate access station during a subsequent frame of the super frame. The method further includes determining whether the detected secondary synchronization channel has a signal strength greater than a threshold signal strength. The method additionally includes receiving permission to begin a cooperative data transfer operation with both the primary access station and the alternate access station.
    Type: Application
    Filed: October 23, 2009
    Publication date: July 8, 2010
    Applicants: Fujitsu Microelectronics Limited, Fujitsu Limited
    Inventors: Dorin Viorel, Masato Okuda, Kevin Power, Luciano Sarperi
  • Patent number: 7750478
    Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: July 6, 2010
    Assignees: Sanyo Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC Corporation
    Inventors: Koujiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino