Patents Assigned to Fujitsu Microelectronics Limited
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Patent number: 7750710Abstract: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase inverting element 9 inverting a phase of the signal, and an adjusting element 10, connected in series to the second delay element 8, to which the signal is propagated, wherein a total of the delay time of the second delay element 8 and the delay time of the adjusting element 10 is adjusted.Type: GrantFiled: November 3, 2005Date of Patent: July 6, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kenichi Nomura
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Patent number: 7742645Abstract: The encoding device of the present invention comprises a type determination unit inputs each bit of the weblet co-efficient in a depth direction in parallel and determines type information indicating which the bit is, the first “1” bit when viewed from an MSB side, a bit located further on the MSB side than the first “1” bit, a bit located further on an LSB side than the first “1” bit, a buffer unit for buffering the determined type information of each bit for each bit depth and a pass determination unit for determining pass information of a type information to process, of a plurality of pieces of type information, based on the plurality of pieces of buffered type information of the same depth.Type: GrantFiled: October 18, 2006Date of Patent: June 22, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Sou Nakamura
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Patent number: 7742469Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.Type: GrantFiled: August 10, 2006Date of Patent: June 22, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kazuyuki Kanazashi
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Publication number: 20100146171Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: ApplicationFiled: December 4, 2009Publication date: June 10, 2010Applicant: Fujitsu Microelectronics LimitedInventor: Yoshihiro TAKEMAE
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Patent number: 7733716Abstract: A signal masking circuit includes a detection circuit, a delayed read data strobe signal generation circuit, a gating circuit, a counting circuit, and a masking circuit. The detection circuit detects a period of a logic “L” of a read data strobe signal. The gating circuit gates a delayed read data strobe signal, and generates a first masked read data strobe signal. The counting circuit counts the falls of the first masked read data strobe signal until the count reaches a predetermined number, and generates a masking signal for masking the first masked read data strobe signal. The masking circuit masks the first masked read data strobe signal, and outputs a second masked read data strobe signal.Type: GrantFiled: May 23, 2008Date of Patent: June 8, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kouji Mizutani
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Patent number: 7733074Abstract: To provide a control circuit of a current mode DC-DC converter, a current mode DC-DC converter and a control method thereof having excellent high-speed responsiveness with respect to fluctuations in output voltage. The control circuit of the current mode DC-DC converter serves as a DC-DC converter 1 that controls a peak value of a coil current and comprises a window comparator that detects whether an output voltage VOUT is within a predetermined voltage range including a target voltage, and a peak current setting unit that sets a peak current setting value of a coil current to a lower limit value or an upper limit value in response to a high or low voltage level of the output voltage VOUT, in the case that the output voltage VOUT is not within the predetermined voltage range including the target voltage.Type: GrantFiled: November 8, 2007Date of Patent: June 8, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Morihito Hasegawa, Takashi Matsumoto, Ryuta Nagai
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Patent number: 7734973Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.Type: GrantFiled: December 29, 2006Date of Patent: June 8, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Takahisa Hiraide, Hitoshi Yamanaka
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Patent number: 7734896Abstract: A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.Type: GrantFiled: March 28, 2006Date of Patent: June 8, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hiroshi Furukawa
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Patent number: 7732925Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.Type: GrantFiled: February 11, 2005Date of Patent: June 8, 2010Assignees: SANYO Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC CorporationInventors: Yoshio Okayama, Akira Suzuki, Koujiro Kameyama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino
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Patent number: 7728370Abstract: A stacked film of a first insulation film being a silicon oxide film with an extremely low moisture content, and a second insulation film being a silicon oxide film with a higher moisture content than the first insulation film, therefore, with a low in-plane film thickness distribution rate is formed, and this is polished by CMP. Polishing is performed until the second insulation film is wholly removed directly above a ferroelectric capacitor structure and a surface of the first insulation film is exposed to some extent. At this time, surface flattening is performed for a top surface of a first portion in the first insulation film and a top surface of the second insulation film, and an interlayer insulation film constituted of the first insulation film and the second insulation film remaining on a second portion of the first insulation film is formed.Type: GrantFiled: November 28, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kazutoshi Izumi
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Patent number: 7729896Abstract: It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.Type: GrantFiled: May 24, 2006Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Masato Tatsuoka, Atsushi Ike
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Patent number: 7728418Abstract: A semiconductor device includes a plurality of chips comprising a plurality of first moisture-proof rings individually surrounding said plurality of chips, a second moisture-proof ring surrounding the entire plurality of chips, and a wire for connecting said plurality of chips to each other.Type: GrantFiled: July 13, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hiroshi Nomura, Satoshi Otsuka, Yoshihiro Takao
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Patent number: 7730232Abstract: A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.Type: GrantFiled: April 25, 2005Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Fujioka, Kotoku Sato, Hitoshi Ikeda, Yoshiaki Okuyama, Jun Ohno
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Patent number: 7729181Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.Type: GrantFiled: January 17, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Keizo Morita, Shoichiro Kawashima
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Patent number: 7729200Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: December 18, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7727843Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.Type: GrantFiled: January 9, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hiroshi Ishihara, Kenji Maruyama, Tetsuro Tamura, Hiromasa Hoko
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Patent number: 7724859Abstract: A synchronizing apparatus comprises a normal lock synchronization detecting unit for detecting synchronization by detecting from demodulated data a synchronization pattern in a normal lock state, and a pseudo lock synchronization detecting unit for detecting synchronization by detecting from the demodulated data a synchronization pattern in a pseudo lock state.Type: GrantFiled: May 31, 2006Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kazuyuki Kanazashi
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Semiconductor device with current mirror circuit having two transistors of identical characteristics
Patent number: 7723796Abstract: A semiconductor device includes a current-mirror circuit including a first ring-shape gate, a second ring-shape gate, a first diffusion layer formed around the first ring-shape gate and the second ring-shape gate, a second diffusion layer formed inside the first ring-shape gate, a third diffusion layer formed inside the second ring-shape gate, an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential, and an STI area formed around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate constitute the current-mirror circuit, wherein gates of dummy transistors that do not function as transistors are situated between the STI area and the first and second ring-shape gates, and are arranged both in a first direction and in a second direction substantially perpendicular to the first direction.Type: GrantFiled: September 24, 2007Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Hiroyoshi Tomita -
Patent number: 7723825Abstract: According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.Type: GrantFiled: October 30, 2006Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Masayoshi Asano, Toru Anezaki, Junichi Ariyoshi
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Patent number: 7725621Abstract: A semiconductor device and data transfer method capable of efficient DMA transfer processing. The device comprises: a sector buffer which temporarily stores data during transfer, the buffer having an I/O port used for DMA transfer with a system bus and having an I/O port used for data transfer with the I/O controller; a switching section which switches whether to connect between the system bus and the I/O controller, or to connect between the sector buffer and the I/O controller or the system bus; and a sector buffer controller which separately starts data transfer through the I/O ports and which, when detecting completion of the data transfer of a transfer unit between the sector buffer and the I/O controller, transmits to the switching section a control signal for cutting off data transfer between the sector buffer and the I/O controller and for connecting the system bus and the I/O controller.Type: GrantFiled: February 16, 2007Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kohei Mutaguchi