Abstract: When a still picture is picked up by a digital camera, the still picture is divided into a plurality of areas and is processed for each area. After the process of one divided area is completed, then the process of a motion picture obtained from an imaging device. After the process of the motion picture is completed, another divided area of the still picture is processed again. Such switching between a motion picture process and a still picture process is performed until the process of the entire still picture is completed. Thus, after a still picture is picked up by a digital camera, a motion picture can be promptly displayed and a live image picked up by the camera can be displayed on a back LCD screen.

Abstract: There is provided a memory access device including: a counter counting based on a value holding a size of data corresponding to a processing region requested from a processor; a second memory coupled between the processor and a first memory where the data corresponding to the processing region is stored; a detector detecting a state of the second memory based on a read pointer and a value of the counter in the second memory; and a controller outputting a transfer request to transfer the data corresponding to the processing region from the first memory to the second memory based on a detection result of the detector.

Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.

Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.

Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

Abstract: A data verification method includes extracting a first graphic and a second graphic from a first circuit pattern, extracting a third graphic and a fourth graphic from a second circuit pattern, the second circuit pattern being in a layer different than a layer including the first circuit pattern; performing transformation on the first graphic; comparing the first graphic having undergone the transformation with the second graphic; performing the transformation on the third graphic; comparing the third graphic having undergone the transformation with the fourth graphic; when the first graphic having undergone the transformation matches the second graphic, and the third graphic having undergone the transformation matches the fourth graphic, performing grouping for the first and second graphics and setting the first graphic as a first representative graphic; and verifying a shape of the first circuit pattern based on the first representative graphic.

Abstract: A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

Abstract: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element.

Abstract: A driver circuit includes an output transistor circuit that includes a first transistor of a first conductivity type and a second transistor of a second conductivity type disposed between a supply voltage source and a reference voltage source, and that outputs an output signal from a connection node between the first transistor and the second transistor, a first pre-buffer circuit that drives a gate of the first transistor in response to an input signal, and a second pre-buffer circuit that drives a gate of the second transistor in response to the input signal.

Abstract: An electric fuse cutoff control circuit controlling cutoff of a plurality of electric fuses including: a cutoff information storage circuit adapted to store cutoff information about whether or not each of the plurality of electric fuses is cut off; a cutoff information control circuit controlling the cutoff of the plurality of electric fuses based on an output signal of the cutoff information storage circuit; and a cutoff information renewal circuit receiving an output signal of the cutoff information control circuit and renewing the cutoff information set for the cutoff information storage circuit.

Abstract: A gain control circuit includes a comparator that compares an input gain value with a count value to generate a comparison result signal, a counter that counts up or counts down the count value in accordance with the comparison result signal, and a gain modulator circuit that modulates the count value to generate a gain control signal which changes in a time-divided manner. The gain modulator circuit modulates the count value so that a gain obtained by time-averaging a gain corresponding to the gain control signal matches a gain based on the count value.

Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Abstract: A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.

Abstract: An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.

Abstract: A power supply includes a first switch and a second switch coupled in series between an input voltage terminal to which an input voltage is applied and a reference voltage terminal to which a reference voltage lower than the input voltage is applied, an inductor disposed between a junction coupling the first and second switches and an output terminal from which an output voltage is output, and a controller controlling the first and second switches to be alternately switched at a given switching cycle depending on an error of the output voltage with respect to a target voltage, wherein the controller changes the switching cycle from a first cycle to a second cycle longer than the first cycle, depending on a voltage at the junction when the second switch is in a turned-on state.

Abstract: An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor.

Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.

Abstract: A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate.

Abstract: A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.