Abstract: An image processing apparatus includes, a color correction unit performing color correction on RGB signals to generate color-corrected RGB signals; a YC conversion unit converting the color-corrected RGB signals into a first luminance signal and a color-difference signal; a Y conversion unit generating a second luminance signal based on the RGB signals; an edge combination unit combining the first luminance signal with the second luminance signal; an edge adjustment unit obtaining an edge-adjusted signal based on a result of the combining by the edge combination unit; and an adder adding the first luminance signal to the edge-adjusted signal.

Abstract: An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.

Abstract: A communication apparatus includes a transmitter for transmitting an outgoing radio signal, a receiver for receiving an incoming radio signal, and a controller for controlling a direct current carrier leakage, and the transmitter includes a first multiplier for multiplying a first carrier-wave signal by an In-phase signal, a second multiplier for multiplying a signal having the similar frequency as and a phase shifted by 90 degree with respect to the first carrier-wave signal by a Quadrature-phase signal, and a transmitting amplifier for amplifying a composite signal multiplied by the In-phase signal and the Quadrature-phase signal, respectively, and outputting the composite signal for forming the outgoing radio signal.

Abstract: A pattern verification apparatus includes a correction section creating a plurality of first data pieces; a determination section performing light intensity simulation to create a plurality of plots, determine whether or not each of the plurality of simulation result plots falls within an allowable range, and recognize two or more simulation result plots which do not fall within the allowable range as a plurality of second data pieces; an extraction section extracting a reference pattern of the plurality of original design patterns corresponding to the plurality of second data pieces; and a classifying section classifying the plurality of second data pieces into categories of the reference pattern.

Abstract: An imaging device includes an image sensing device provided on a semiconductor substrate; a transparent member provided on a light-receiving area of the image sensing device; and a circuit element provided on the transparent member, wherein the image sensing device and the circuit element are electrically coupled to each other.

Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.

Abstract: A layout verification method for verifying a layout of a semiconductor device by a computer having a memory storing layout data and information of operation conditions for a plurality of operation modes in which the semiconductor device is expected to assume during its testing and practical use, the semiconductor device including a semiconductor substrate of one conductivity type, a plurality of wells accommodating at least one of the circuit elements and being applicable to a plurality of different bias voltages in dependence of the operation modes, the method includes specifying combination of all the adjacent pairs of the wells located adjacently to each other within the semiconductor substrate, and the distance of each of all the adjacent pairs of the wells in reference to the layout data, determining, for each of the wells.

Abstract: A lookup table includes a single via layer having 2N via insertion portions corresponding to 2N input patterns provided from N input terminals; and a via inserted into at least one of the via insertion portions, the via connecting the input terminal and an output terminal.

Abstract: A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.

Abstract: A DC-DC converter control circuit includes: a slope signal generation circuit that generates a reference voltage by superimposing a slope voltage onto a standard voltage; a comparator that performs comparison of the reference voltage with an output voltage and generates a signal according to a result of the comparison; an oscillator that generates a pulse signal with a substantially constant cycle; and a control signal generation circuit that generates a control signal that turns on a switch based on a comparator output signal and turns off the switch based on the pulse signal.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

Abstract: A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings, a second signal generator that generates a third signal having a delay relative to the first signal, and a detector that detects, when a state of the third signal changes, a delay state of a signal based on the states of the second signals, wherein the first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state.

Abstract: A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.

Abstract: An image processing method performed by a processor for processing a plurality of pixel values in an image data representing a two-dimensional image, the image processing method including defining a block representing a part of the two-dimensional image corresponding to a predetermined number of pixels in rows and columns, obtaining an average of a gradient of pixel value on the basis of the pixel values of adjacent pixels in the block along each of at least one of rows and at least one of columns, generating a product of the average of the gradient pixel value along each of at least one of the rows and the average of the gradient pixel value along each of at least one of the columns, and generating a double summation of the products of the gradient pixel values of each of the rows and the columns.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A ?? modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators.

Abstract: An image processing apparatus includes an image pickup circuit that performs photoelectric conversion on an optical image, and a chromatic aberration correcting circuit that calculates an amount of shift by chromatic aberration based on a linear function to perform chromatic aberration correction on captured image data in accordance with the amount of shift. The chromatic aberration correcting circuit performs the chromatic aberration correction on a first pixel in a first area including an optical center of the captured image data with a first linear function using a distance from the optical center, and performs the chromatic aberration correction on a second pixel in a second area that does not include the optical center and that is different from the first area with a second linear function using the distance from the optical center.

Abstract: A semiconductor integrated circuit includes: a first switching element and a second switching element that are provided in series between a first power line and a second power line; a power supply circuit that outputs a given output voltage by on/off controlling the first switching element and the second switch element; a current detection circuit that detects a current corresponding to an output load current of the power supply circuit; a switching time control circuit that controls a switching time defined by a power supply voltage and the output voltage based on a current value detected by the current detection circuit; and a switching element control circuit that controls the first switching element and the second switching element based on an output signal of the switching time control circuit.

Abstract: A memory access determination circuit includes a counter that outputs a first value counted by using a first reference value, and a control unit that makes a cache determination of an address corresponding to an output of the counter, wherein, when a cache miss occurs for the address, the counter outputs a second value by using a second reference value.