Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.

Abstract: A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are connected to form first reticle data. Reticle pattern data having data representing binding portions serving as light blocking portions is formed. The front edge portions being adjacent to each other and aligned in the X-axis are connected and adjacent joints being aligned in the same manner as the front edge portions are also connected to form second reticle data. Then, portions are provided at central regions between the binding portions so as to connect the adjacent binding portions including the front edge portions and the joints. Then, reticle data having data representing the binding portions serving as transparent patterns is formed.

Abstract: An interface device and interface device control method that switches a transmission rate to enable high-speed transmission when necessary. In devices (nodes) provided with an interface device, a transmission rate control circuit decreases the frequency of a clock signal to only enable low-speed transmission operations during low-speed transmission and when a transfer operation is not being performed. A node requiring switching to a high-speed transmission rate negotiates with each node included in a route to a transfer destination and reads the device information stored in the register to confirm whether or not each node has a transmission capacity applicable for high-speed transmission. Then, when the transmission capacity is applicable for high-speed transmission, the transmission rate control circuit increases the frequency of the clock signal to change the operating speed of its node and each of the nodes requiring the switching of the transmission rate to high-speed transmission.

Abstract: A method for a computer setting up a terminal layer of a semiconductor circuit having plural wiring layers including obtaining various kinds of information such as placement information relating to a plurality of cells or macros of the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with the cell or macro at a connecting destination; and setting up a terminal layer based on a result of the comparing.

Abstract: An output buffer circuit that suppresses the generation of an erroneous operation signal during power activation includes a first level converter generating a first signal based on a data input signal having an amplitude range between a first power supply potential and a ground reference potential. The first signal has an amplitude range between a second power supply potential, which differs from the first power supply potential, and the ground reference potential. A second level converter generates a second signal having an amplitude range between the second power supply and ground reference potentials based on a control input signal having an amplitude range between the first power supply and ground reference potentials. The first signal falls with a delay from the second signal. An output circuit generates an output signal. A timing adjustment circuit compensates for the fall delay of the first signal during power activation.

Abstract: A method for a design support is provided. The method includes a computer that executes processes of detecting a combination of vias comprising a target via and a neighboring via-; calculating a distance between the combination of the target via and the neighboring via, replacing a shape of the target via and a shape of at least one of the neighboring via with a shape of an exposure pattern of the via, searching the adjacent wiring arranged within the distance between the vias or less from a position of the target via after the process of replacing, and converting the position of the neighboring via to which the process of replacing is applied to the position searched by the process of searching and storing the position in the database; and outputting the layout data converted by the process of converting.

Abstract: Control circuitry, comprising: first control means operable to generate a first control signal, the first control signal being indicative of a relationship between an output signal and a first reference signal, and to generate said output signal in dependence upon said first control signal, the first control means being configured to tend to maintain a first desired relationship between the output signal and the first reference signal in response to said first control signal; and second control means configured to influence operation of said first control means in response to said first control signal by way of a second control signal so as to tend to maintain a second desired relationship between said first control signal and a second reference signal.

Abstract: A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal from a test apparatus. A dummy defect output unit outputs a dummy defect signal during a predetermined period of time after the defect detection input unit receives the defect detection signal. A data output unit inverts a logic of the read data output from the read unit during an activation of the dummy defect signal. Accordingly, an artificial defect can be generated by the semiconductor memory without changing the test apparatus or a test program. As a result of this, a relief efficiency can be enhanced and a test cost can be reduced.

Abstract: A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor.

Abstract: For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Abstract: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element.

Abstract: A communication system is provided which is capable of easily setting a transmission speed between a signal transmitter and a signal receiver to carry out information communication. A transmitting device transmits one frame of measuring data which contains a start bit to be added to a head of the data and a stop bit to be added to an end of the data and which is used for a signal receiver to measure a transmission speed. A framing error detector in a receiving device receives the measuring data for detection, at every measuring point, of a framing error which occurs when a transmission speed of the signal transmitter does not coincide with a transmission speed of the signal receiver and normal detection of a stop bit is impossible and generates information about detection of a framing error. A transmission speed measurer measures a transmission speed of the transmitting device based on information about detection of a framing error and measuring point interval time.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

Abstract: A control circuit for a power supply device, a power supply device, and the like are provided in which the power supply device has a plurality of DC/DC converters provided for generating voltage while the mutual relationship of potential between the voltage outputs is maintained. The control circuit 20 in the power supply device 10 which outputs different direct current voltages (VCC, VBGP, and VBGN) includes a voltage setting unit 22 for determining the setting level of a second direct current voltage VBGP which has a potential relationship with the setting level of the first direct current voltage VCC which is one of a plurality of the different direct current voltages.

Abstract: According to an embodiment, a DC-DC converter comprises: an error amplifier that receives a soft start signal and amplifies a difference between an output voltage signal and a reference voltage signal; a PWM control circuit that controls ON and OFF states of a first switching transistor and a second switching transistor based on the output of the error amplifier; a frequency divider that divides a frequency signal and outputting a divided frequency signal; an accumulator that performs an adding operation based on the divided frequency signal and a control signal; and a DA converter that generates the soft start signal based on an output of the accumulator.

Abstract: A semiconductor integrated circuit includes a check unit which compares a value of a pixel of interest with values of neighboring pixels contained in an image signal supplied from an image sensor, and determines based on the comparison whether the pixel of interest is defective, and a defect correcting unit which corrects the value of the pixel of interest by using values of surrounding pixels in response to the determination by the check unit that the pixel of interest is defective.

Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.

Abstract: A level converter includes a cross-coupled section for holding data and a first switching section connected in series with the cross-coupled section and supplied with a differential input signal. The level converter has a second switching section, a current mirror connection section, a third switching section, and an input/output matching evaluation section. The second switching section is connected in parallel with the cross-coupled section, and the current mirror connection section is connected in a current-mirror configuration with a transistor in the second switching section. The third switching section is connected in series with the current mirror connection section, and the input/output matching evaluation section is used to control a transistor in the third switching section by receiving the input signal and an output node signal.

Abstract: A method for fabricating a photomask includes the steps of forming a phase shift layer, a light-shielding layer, and a negative resist layer in that order on a transparent substrate, forming a first resist pattern including a pattern corresponding to a transfer pattern by performing first exposure and development on the negative resist layer, forming a light-shielding pattern by etching the light-shielding layer using the first resist pattern as a mask, removing the first resist pattern, and then forming a positive resist layer thereon, forming a second resist pattern including a pattern corresponding to a light-absorbing pattern by performing second exposure and development on the positive resist layer, and forming a phase shift pattern by etching the phase shift layer using the second resist pattern as a mask.