Abstract: A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.

Abstract: A semiconductor device with a structure having superior heat sink characteristics. A first heat sink member is located over a wiring board by using an adhesive material. A semiconductor element is stuck over the first heat sink member by using an adhesive material. The semiconductor element and electrodes located over the wiring board are connected by wires. A second heat sink member which covers the semiconductor element and the wires is joined to the first heat sink member by using a conductive adhesive material. The inside and outside of the second heat sink member are sealed by resin except a flat top thereof. By doing so, the semiconductor device is fabricated. Heat which is generated in the semiconductor element and which is transmitted to the first heat sink member is released from an edge portion of the first heat sink member.

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.

Abstract: An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.

Abstract: A power supply voltage detection circuit is provided including: a first switch to connect between a power supply voltage terminal and a first terminal according to a power supply voltage detection signal and an external signal; a second switch to connect between a reference potential terminal and a second terminal according to the power supply voltage detection signal and the external signal; a first resistance connected between the second terminal and the power supply voltage terminal; and a third switch connecting between the first terminal and the reference potential terminal according to a voltage of the second terminal; and an output circuit outputting the power supply voltage detection signal based on a signal from the first terminal.

Abstract: An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.

Abstract: An electrical fuse circuit including: a capacitor composing an electrical fuse; a write circuit breaking an insulating film of the capacitor by applying voltage to between both terminals of the capacitor in accordance with a write signal; and a precharge circuit precharging with respect to the terminal of the capacitor, is provided.

Abstract: Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.

Abstract: A method and circuit for suppressing the generation of unnatural vertical streaks in output image data. A detection processing circuit generates a first noise correction value based on first and second noise detection signals from an OB region. A correction processing circuit performs an offset process on a first noise correction value to generate a second noise correction value and performs an FIR filter process on the second noise correction value to generate a noise correction signal NC. The correction processing circuit then corrects the effective image signal from the effective image region using the noise correction signal and performs a horizontal LPF process on the corrected effective image signal to generate output image data.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the substrate, between the electronic component and the substrate, flow-casting the adhesive on the substrate by a flow-casting unit, in such a manner that the expression S1/S0>1 is satisfied, where S0 is the total contact surface area with the substrate of the adhesive supplied to the substrate, and S1 is the total contact surface area with the substrate of the adhesive after the flow-casting, and curing the adhesive while making the adhesive contact with the electronic component and the substrate in a state where the bumps are abutted against the bonding pads.

Abstract: A semiconductor device includes a first analog circuit (53) adapted to a first performance, and a second analog circuit (55) realizing a second performance higher than the first performance by cooperating with the first analog circuit. It becomes possible to switch circuit characteristics appropriately in accordance with a requested performance while suppressing an increase of a circuit scale, by operating the first analog circuit and interrupting a power supply to the second analog circuit when the first performance is requested, and by operating the first analog circuit and the second analog circuit together when the second performance is requested to thereby share the first analog circuit.

Abstract: An image sensor has a plurality of pixels each with a photoelectric conversion element and a detection transistor the threshold voltage of which fluctuates in accordance with electrical charge generated in the photoelectric conversion element. The image sensor includes a second conductivity type shield region and a first conductivity type photoelectric conversion region; a first conductivity type well region linked to the photoelectric conversion region; a ring-like gate electrode; a second conductivity type source region at the inside of the ring-like gate electrode; a second conductivity type drain region. The image sensor further includes a potential pocket region that is formed in the well region below the ring-like gate electrode and accumulates the electrical charge, wherein the width of the gate electrode is formed narrower in the part adjacent to the photoelectric conversion region than in other parts.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: A DC-DC converter and first and second bypass switch circuits are provided in parallel between an input pin and first and second output pins and operate in accordance with a combination of the voltage value of the input pin and the voltage value required for the first output pin. A start control circuit causes the DC-DC converter to operate unconditionally in a step-down mode during the period from when the DC-DC converter is started until the output voltage of the DC-DC converter becomes equal to the voltage of the input pin. An output slope control circuit synchronizes rising slopes of the output voltages of the first and second bypass switch circuits with a rising slope of the output voltage of the DC-DC converter.

Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.

Abstract: A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list; a creating unit that creates a second verification-item list in which each of the verification items is formed with the functional description and the sequential description about an output action of the verification target; and a converting unit that converts the first verification-item list into a third verification-item list having a same format as the second verification-item list, based on the second verification-item list and the keyword.

Abstract: A mold includes a pot for accommodating resin, a cavity for accommodating a semiconductor chip to be resin-molded and a runner as a resin passage for transporting the resin accommodated in the pot to the cavity. A foreign matter retention pocket is disposed which is a recess formed by digging further a partial inner surface of the runner. A runner magnet attracts and attaches a metallic foreign matter contained in fluid transported in the runner to the inner surface of the foreign matter retention pocket.

Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.