Abstract: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

Abstract: To enable measurement of a suspension position and a suspension period of the reference clock of a microcomputer to be inspected, based on the information stored into a clock information register section, by acquiring output data output from the microcomputer; preserving the acquired output data into a data bank section by use of the reference clock being output from the microcomputer together with the output data; discriminating the suspension of the reference clock by a clock operation discrimination section at sampling intervals of the output data; and writing and preserving the discrimination result into the clock information register section by a register control section.

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

Abstract: An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.

Abstract: A semiconductor device temperature sensor produces a reference level for temperature detection from two or more reference levels of different temperatures to detect a temperature. The temperature sensor is applied for detecting the temperature of a semiconductor storage device having a memory unit which requires a refresh action. A refresh cycle control circuit provided in the semiconductor storage device controls the cycle of the refresh action for the memory unit in response to an output of the temperature sensor.

Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.

Abstract: Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.

Abstract: A method for implementing an in-band relay scheme includes establishing a connection between a base station and a relay station and between the relay station and a mobile station using a frequency. The method also includes receiving data from the base station during a frame via the frequency, the frame comprising a downlink sub-frame, and an uplink sub-frame, wherein the data is received during a beginning portion of the downlink sub-frame. The method further includes transitioning from receive to transmit during the downlink sub-frame. The method additionally includes transmitting data, received from the base station during a previous frame, to the endpoint during a later portion of the downlink sub-frame via the frequency. The method also includes transmitting data received from the endpoint during a previous frame, to the base station during a beginning portion of the uplink sub-frame via the frequency. The method further includes transitioning from transmit to receive during the uplink sub-frame.

Abstract: A method for implementing an out-of-band relay scheme includes establishing a relay connection between a base station and a relay station using a relay frequency and an access connection between the relay station and an endpoint using an access frequency that is different than the relay frequency. The method also includes receiving at the relay station data from the base station during a current frame via the relay frequency and data from the endpoint during the current frame via the access frequency. At least a portion of the data from the endpoint is received concurrently with data from the base station. The method additionally includes transmitting previously received data from the relay station to the base station during the current frame via the relay frequency and to the endpoint during the current frame via the access frequency. At least a portion of the data transmitted to the endpoint is transmitted concurrently with data transmitted to the base station.

Abstract: 2n data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2n data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2n data transfer signal lines.

Abstract: A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

Abstract: A semiconductor device includes a first multilayer interconnection structure formed on a substrate and a second multilayer interconnection structure formed on the first multilayer interconnection structure, wherein the first multilayer interconnection structure includes a pillar extending from a surface of the substrate and reaching at least the second multilayer interconnection structure.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.

Abstract: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic. On the hydrophilic surface of the first film, a second film is formed which is an insulating film made of a low dielectric constant insulating material having a relative dielectric constant of 2.7 or smaller or an insulating film made by a coating method. A sufficient adhesion property is obtained when a film made of low dielectric constant insulating material is formed on an insulating film made of silicon carbide having a small amount of oxygen contents.