Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A communication system is provided which is capable of easily setting a transmission speed between a signal transmitter and a signal receiver to carry out information communication. A transmitting device transmits one frame of measuring data which contains a start bit to be added to a head of the data and a stop bit to be added to an end of the data and which is used for a signal receiver to measure a transmission speed. A framing error detector in a receiving device receives the measuring data for detection, at every measuring point, of a framing error which occurs when a transmission speed of the signal transmitter does not coincide with a transmission speed of the signal receiver and normal detection of a stop bit is impossible and generates information about detection of a framing error. A transmission speed measurer measures a transmission speed of the transmitting device based on information about detection of a framing error and measuring point interval time.

Abstract: A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal from a test apparatus. A dummy defect output unit outputs a dummy defect signal during a predetermined period of time after the defect detection input unit receives the defect detection signal. A data output unit inverts a logic of the read data output from the read unit during an activation of the dummy defect signal. Accordingly, an artificial defect can be generated by the semiconductor memory without changing the test apparatus or a test program. As a result of this, a relief efficiency can be enhanced and a test cost can be reduced.

Abstract: A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

Abstract: A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.

Abstract: A method for fabricating a photomask includes the steps of forming a phase shift layer, a light-shielding layer, and a negative resist layer in that order on a transparent substrate, forming a first resist pattern including a pattern corresponding to a transfer pattern by performing first exposure and development on the negative resist layer, forming a light-shielding pattern by etching the light-shielding layer using the first resist pattern as a mask, removing the first resist pattern, and then forming a positive resist layer thereon, forming a second resist pattern including a pattern corresponding to a light-absorbing pattern by performing second exposure and development on the positive resist layer, and forming a phase shift pattern by etching the phase shift layer using the second resist pattern as a mask.

Abstract: According to an embodiment, a DC-DC converter comprises: an error amplifier that receives a soft start signal and amplifies a difference between an output voltage signal and a reference voltage signal; a PWM control circuit that controls ON and OFF states of a first switching transistor and a second switching transistor based on the output of the error amplifier; a frequency divider that divides a frequency signal and outputting a divided frequency signal; an accumulator that performs an adding operation based on the divided frequency signal and a control signal; and a DA converter that generates the soft start signal based on an output of the accumulator.

Abstract: A semiconductor integrated circuit includes a check unit which compares a value of a pixel of interest with values of neighboring pixels contained in an image signal supplied from an image sensor, and determines based on the comparison whether the pixel of interest is defective, and a defect correcting unit which corrects the value of the pixel of interest by using values of surrounding pixels in response to the determination by the check unit that the pixel of interest is defective.

Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.

Abstract: A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.

Abstract: A level converter includes a cross-coupled section for holding data and a first switching section connected in series with the cross-coupled section and supplied with a differential input signal. The level converter has a second switching section, a current mirror connection section, a third switching section, and an input/output matching evaluation section. The second switching section is connected in parallel with the cross-coupled section, and the current mirror connection section is connected in a current-mirror configuration with a transistor in the second switching section. The third switching section is connected in series with the current mirror connection section, and the input/output matching evaluation section is used to control a transistor in the third switching section by receiving the input signal and an output node signal.

Abstract: A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals, and a refresh-target selecting circuit configured to successively select all the primary word lines and all the one or more redundant word lines one by one in response to the respective pulses of the refresh timing signal, wherein a refresh operation is performed with respect to the word lines that are successively selected by the refresh-target selecting circuit.

Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

Abstract: A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask.

Abstract: A semiconductor memory device includes a memory cell array, a redundant element, an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal, a decoder circuit configured to select the redundant element in response to an externally applied address that matches the redundancy address selected by the address specifying circuit, and a test mode setting circuit configured to change the switchover signal in response to an externally applied input, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses.

Abstract: A noise reduction device includes a line buffer that stores a blend value obtained by blending a pixel value stored in the line buffer with a processing target pixel value at a given ratio by an amount of one line of an image, and a selector that selects the blend value when a difference between the blend value in the line buffer and the target pixel value is less than a threshold, and that selects the target pixel value when the difference is greater than or equal to the threshold.

Abstract: An encryption/decryption circuit includes a swap circuit for outputting each of text data and initialization vector data which are input from an input terminal to either a first or second output terminal in accordance with one of modes of operation, an encryption/decryption processing unit to which one of the text data and the initialization vector data are input from the first output terminal and which performs encryption processing and decryption processing on the data, and an exclusive OR processing unit to which another one of the initialization vector data and the text data are input from the second output terminal and which performs an exclusive OR operation on the data.

Abstract: A semiconductor device includes a circuit section having an output impedance which changes in accordance with a switching signal for switching between drive capabilities, and transforming an input signal into an output signal in accordance with the output impedance, a reference voltage generating section generating a reference voltage in accordance with the switching signal and the input signal, and a comparing section comparing a voltage of the output signal to the reference voltage.

Abstract: A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.

Abstract: A method for manufacturing a semiconductor device by mounting a semiconductor element on a circuit board, the semiconductor element having a first electrode made of a first material on a semiconductor substrate, the circuit board having a second electrode made of a second material on an insulating substrate, the method includes forming a connecting member on the first electrode, a melting point of the connecting member being lower than a melting point of the first material, placing the semiconductor element on the circuit board, so as to face the connecting member toward the second electrode, and connecting the first electrode and the second electrode, so as to interpose the connecting member between the first electrode and the second electrode, at a temperature that is lower than the melting point of the first material and higher than the melting point of the connecting member.