Abstract: A circuit for controlling charging includes a transistor provided on a charging path between a position of a charging terminal and a position of a battery, an input voltage detecting circuit configured to detect a potential of a point on the charging path coupled to the charging terminal's side of the transistor, and a drive circuit configured to control an ON resistance of the transistor between a conductive state and a nonconductive state in response to the potential detected by the input voltage detecting circuit.

Abstract: A coding/decoding part performs codes and decodes a given signal in one of a plurality of coding/decoding modes of different bit rates; and a control part sets a predetermined bit rate to be applied by the coding/decoding part in case a given signal is output after being coded and decoded by said coding/decoding part without storage thereof in a predetermined recording medium.

Abstract: A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor.

Abstract: Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on.

Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.

Abstract: An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.

Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.

Abstract: A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.

Abstract: A program circuit activates a pass signal when a first program unit is programmed. The first program unit is programmed when a test of an internal circuit is passed. A mode setting circuit switches an operation mode to a normal operation mode or a test mode by external control. A state machine allows a partial circuit of the internal circuit to perform an unusual operation different from a normal operation when the pass signal is inactivated during the normal operation mode. By recognizing the unusual operation during the normal operation mode, it can be easily recognized that a semiconductor integrated circuit is bad. Since a failure can be recognized without shifting to the test mode, for example, a user who purchases the semiconductor integrated circuit can also easily recognize the failure.

Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Abstract: A noise removal circuit in an image signal includes a boundary determination unit configured to determine a position of a light-dark boundary on the basis of, or as a function of, a pixel value of a plurality of surrounding pixels, and a selection filter configured to perform filtering in a range of the plurality of surrounding pixels which belong to a range which does not cross a boundary determined by the boundary determination unit.

Abstract: Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.

Abstract: In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.

Abstract: A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray includes a lowermost tray and an uppermost tray interposing therebetween an intermediate tray. The lowermost and uppermost trays and are each of a circular shape having a diameter D1. A diameter D3 of the intermediate tray is smaller than the diameter D1. The intermediate tray is centrally formed with a screw hole portion in which a locking spacer screw is screwed. A semiconductor package is to be placed in a package holding pocket. With the locking spacer screw, the intermediate is slidable in an X and Y directions, so that the X and Y coordinates of the semiconductor package are determined uniquely relative to the carrier tray.

Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.

Abstract: An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.