Abstract: A method of performing optical proximity effect correction includes defining a partial area of an entire area of a mask pattern, the mask pattern including a real pattern and a dummy pattern, and performing optical proximity effect correction only with respect to the partial area.

Abstract: In performing exposure for forming patterns being fine as well as having great density difference, adequate corrections are to be enabled for suppressing the influence from peripheries of these patterns to be a minimum and for suppressing the dimension variation within the plane of semiconductor substrate or among semiconductor substrates to a minimum. So-called lower-layer corrections are executed, in order to suppress the three-dimensional influence, namely the influence of the film-thickness distribution of a lower-layer structure body lying under a subject film to be processed with a resist. A pattern-correcting portion adjusts the amount of exposure such that it cancels the in-plane film-thickness distribution of the lower-layer structure body in respective exposure regions.

Abstract: A method for calculating a tolerable value for simultaneous switching noise in an input/output circuit having a differential input supplied with a power supply voltage. The method includes providing an input/output circuit having a differential input unit with a pulse signal of a predetermined duty ratio, setting a tolerable range for the duty ratio of the output signal of the input/output circuit with respect to the pulse signal, changing the power supply voltage supplied to the differential input unit of the input/output circuit, measuring the duty ratio of the output signal corresponding to the voltage change, comparing the measured duty ratio with the tolerable range, and calculating a tolerable value for the simultaneous switching noise.

Abstract: A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line at least during a standby period when the memory cell is not accessed. A substrate voltage of an nMOS transistor with source or drain connected to the bit line is set to the low level voltage or lower of the word line. Therefore, when the word line and the bit line fails short and the voltage of the bit line changes to the low level voltage of the word line during the standby period, a substrate current can be prevented from flowing between the source of the nMOS transistor and a substrate or the drain and the substrate.

Abstract: When adopting a stack-type capacitor structure for a ferroelectric capacitor structure (30), an interlayer insulating film (27) is formed between a lower electrode (39) (or a barrier conductive film) and a conductive plug (22) to eliminate an impact of orientation/level difference on a surface of the conductive plug (22) onto the ferroelectric film (40). Differently from a conductive film like the lower electrode (39) or the barrier conductive film, the interlayer insulating film (27) can be formed without inheriting the orientation/level difference from its lower layers by planarizing the surface thereof.

Abstract: A host apparatus that adjusts consumption of a device in accordance with the power supply capability of the host apparatus. The host apparatus includes a plurality of communication ports and devices connected to each communication port. A host controller of the host apparatus communicates with the devices to acquire equipment information including the consumption current of each device. A current supply circuit supplies current to the devices connected to the communication ports. An MPU changes the current supplied from the current supply circuit to the plurality of devices when a total value of the consumption current of a device newly connected to the plurality of communication ports and the consumption current of each device for which connection with the plurality of ports has already been recognized exceeds the current that the current supply circuit is capable of supplying.

Abstract: A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.

Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Abstract: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.

Abstract: An automatic gain control circuit generates, based on comparison between an average brightness of brightness data output for each frame from an image sensor and a target brightness, an integration time adjustment signal for adjusting an integration time during which the image sensor is exposed, a gain adjustment signal for adjusting gain of an amplifier that amplifies an output signal of the image sensor, and a frame rate adjustment signal for changing a frame rate. The automatic gain control circuit includes an exposure control circuit for adjusting a blanking time of each frame and generating, as the frame rate adjustment signal, a maximum integration time adjustment signal for switching a maximum integration time of the image sensor.

Abstract: A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.

Abstract: It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference between the comparison target signals COMP1 and COMP2 to the control terminal of a tri-state buffer, based on a signal synchronous with the start-up of the comparison target signal COMP1 detected by an edge detection flag generation circuit and a signal synchronous with the start-up of the comparison target signal COMP2 detected by an edge detection flag generation circuit. A status management circuit outputs a signal A_SIGNAL corresponding to the phase advance or delay of the comparison target signals COMP1 and COMP2 to the input terminal of the tri-state buffer.

Abstract: A peripheral circuit control register has a plurality of bits corresponding respectively to peripheral resources. A decoder activates an access signal to the peripheral resource at an access destination when the bit corresponding to the peripheral resource at the access destination in the peripheral circuit control register is under a set state in response to occurrence of access to any of the peripheral resources by a CPU. A functional specification of an evaluation chip can be made equivalent to those of product chips and development of a wrong user program can be prevented by setting in advance the bits of the peripheral circuit control register corresponding to the peripheral resources mounted to the product chip to the set state.

Abstract: An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode.

Abstract: A ferroelectric capacitor formation method necessary for stably fabricating an FeRAM and a semiconductor device fabrication method. After a PZT film is deposited on a lower electrode layer, the PZT film is crystallized by performing heat treatment in an atmosphere of a mixed gas which contains O2 gas and Ar gas. In this case, the flow rate of the O2 gas is controlled by one mass flow controller. The flow rate of the Ar gas used for purging and the flow rate of the Ar gas used for adjusting O2 gas concentration are controlled by different mass flow controllers. Before raising the temperature, the O2 gas, the Ar gas used for purging, and the Ar gas used for adjusting O2 gas concentration are made to flow at predetermined flow rates. Only the Ar gas used for purging is stopped, raising the temperature is begun, and the heat treatment is performed. At this time the O2 gas and the Ar gas used for adjusting O2 gas concentration flow at the predetermined flow rates.

Abstract: A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array. When a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, according to which the access operation is performed.

Abstract: An image processing apparatus capable of controlling the amount of codes in the image data of one image through one-pass encoding, without changing a quantization table. A Discrete Cosine Transformation (DCT) unit performs discrete cosine transformation on each MCU of the image data of the image. A quantizer quantizes DCT coefficients resulted from the discrete cosine transformation, using the quantization table. A code amount controller sets a threshold value for each MCU based on a target amount of codes for one image and the amount of codes usable for the unprocessed MCUs, reduces the quantized DCT coefficients based on the threshold value, in order to adjust the amount of codes to be generated in the MCU.

Abstract: In order to execute desired operation on data to be processed of each data series to output processed data, a processing unit changes an arithmetic processing function by establishing a connection relation of internal components according to connection information. In each processing cycle, a control unit executes control processing to pieces of instruction information in a predetermined sequence and outputs, as connection information, an assignment of the components thereof obtained in the control processing. The control processing is to determine the components of the processing unit to be assigned to an operation when the operation indicated by the instruction information is executable, and to shift a processing cycle in which the operation is executed to a subsequent processing cycle, upon satisfying a data output timing of an output buffer unit, when the operation indicated by the instruction information is unexecutable due to lack of the components of the processing unit.

Abstract: A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

Abstract: A network switching device is provided for enabling priority control of packets, enhancing the using efficiency of a buffer for storing a received packet, and reducing the costs of components. The received packet is stored in the corresponding buffer with information of the packet under the control of a buffer controller. Further, a priority determining circuit is also provided for determining a priority class and a destination of the received packet. The buffer controller creates a transmit queue to which the packets of priority classes are to be registered in each buffer. When writing the received packet in the buffer, the buffer controller is served to reserve the received packet for transmission next to the last registered one of the packets of the same priority class registered in the corresponding transmit queue based on the determination of the priority determining circuit.