Abstract: A semiconductor device verification system capable of verifying operation with great accuracy. A pattern matching verification system outputs interference pattern information. A physical verification system compiles the interference pattern information and a design rule and extracts a design rule applied to the interference pattern information. The physical verification system then refers to the design rule to verify a compared cell list and the interference pattern information. As a result, the physical verification system can perform physical verification of layout data without skipping data regarding the compared cell list.

Abstract: A read unit reads a plurality of pieces of image data from an image storing unit for output, respectively. A destination specifying unit specifies image display units to be display destinations of the image data from the read unit. A divided-period setting unit divides a unit display period of the image display units to a plurality (2) of divided periods to correspond to the image display units. In each divided period, a synthesis unit synthesizes, for sequential outputs, the image data from the read units according to the display destination specified by the destination specifying unit in order to multiplex the image data to be displayed on each of the image display units. A separating unit separates, in every divided period of the unit display period, the synthesized image data for output to the image display units corresponding to the respective divided periods.

Abstract: It is an aspect of the embodiments discussed herein to provide a semiconductor device layout method and a semiconductor device layout program that enable the minimum necessary decoupling capacitances to be placed efficiently according to a circuit configuration, placement positions, operation timings, and clock tree of functional circuits.

Abstract: A DC-DC converter for generating a stable output voltage and being applicable to a transient load fluctuation. The DC-DC converter detects an input current, and compares the input current with a rated current of an external power supply. The DC-DC converter controls a positive charging current that is supplied to a secondary battery in accordance with a consumption current of a load so that the input current does not exceed the rated current. The DC-DC converter further controls a negative charging current that is supplied from the secondary battery to the load when the load requires an input current exceeding the rated current.

Abstract: A semiconductor memory device which has a normal memory cell array and a redundant memory cell array for replacing a failure bit in the normal memory cell array, having: a memory cell array having a plurality of word lines, a plurality of bit line pairs crossing the word lines, and a plurality of memory cells placed at the crossing positions; and a plurality of sense amplifier circuits which are placed between adjacent memory cell arrays and are shared by bit line pairs of memory cell arrays on both sides. And a current interrupting circuit for disconnecting the sense amplifier and the bit line pairs in a column having a failure is formed respectively between the sense amplifier circuit and the bit line pairs on both sides. By this current interrupting circuit, short-circuit current from the sense amplifier circuit to the shorted area can be suppressed.

Abstract: This invention provides a semiconductor memory device in which standby current is suppressed to a small level. A ROM device includes memory cells for reading data corresponding to impedance between a terminal connected to bit lines and a source terminal and source power lines connected to the source terminal. In this ROM device, bias voltage is applied between the terminals of selected memory cells.

Abstract: The present invention efficiently suppresses a false defect and realizes reticle inspection where a defect can be detected with high detection sensitivity. In a reticle inspecting method, reticle inspection data generated based on reticle design data is captured. Also, drawing position accuracy measurement data of the reticle is captured to obtain a first correction amount for correcting a position accuracy component of the reticle. Based on the first correction amount, the inspection data is corrected. Based on the corrected inspection data, a defect on the reticle is detected.

Abstract: A differential amplifier circuit of simple circuit configuration is disclosed, which is capable of releasing an output signal within a voltage range independent of the voltage range of a differential input signal. The differential amplifier circuit 1 includes: NMOS transistors N1, N2 that constitute a first differential pair configured to input a differential input voltage; a resistor element Ra connected to drain terminals X1, X2 of the NMOS transistors N1, N2; an op-amp OP having input terminals connected to the drain terminals X1, X2; and NMOS transistors N3, N4 that constitute a second differential pair configured to input an output voltage of the op-amp OP and a reference voltage. The drain terminals of the first differential pair are connected to drain terminals, respectively, of the second differential pair.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.

Abstract: A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.

Abstract: Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on.

Abstract: A camera module includes a module structure constituted by a lens unit to which an image pickup lens is attached and a package to which an imaging element is attached so as to be opposite to the image pickup lens. An optical filter is arranged between the imaging element and the image pickup lens. A portion of a flat surface of the optical filter is fixed to a filter fixing portion via an adhesive. The optical filter is adhered to the filter fixing portion in a state in which an end portion formed by a side surface of the optical filter and the flat surface is in noncontact with the filter fixing portion or the adhesive. Minute particles generated from a cut surface of the optical filter fall outside the filter fixing portion.

Abstract: An exposure mask 24, includes a quartz (transparent) substrate 20, a film 21 formed on the quartz substrate 20, a rectangular main feature 21a formed in the film 21, a first assist feature 21b formed in the film 21 away from the main feature 21a and having a size that is not resolved as a rectangle that has a long side 21e opposing to one side 21d of the main feature 21d, and a second assist feature 21c formed in the film 21 and positioned on a virtual prolonged line L of a diagonal of the main feature 21a and having a size that is not resolved.

Abstract: A semiconductor device fabrication method in which when a semiconductor device with a built-in light receiving element is fabricated, a section for dividing the light receiving element is protected from damage caused by, for example, etching. An antireflection coating is formed not only on a light receiving area in a divided photodiode area but on a division area including a junction area between a division section outside the light receiving area for dividing a photodiode and a cathode. A polycrystalline silicon film is formed so as to cover the antireflection coating. Accordingly, the antireflection coating on the junction area between the division section outside the light receiving area and the cathode is protected against, for example, etching by the polycrystalline silicon film. As a result, the appearance of a crystal defect, a change in impurity concentration, or the like is suppressed in this area.

Abstract: In a performance analyzing apparatus, a setting unit sets an event of which the performance is desired to be monitored, a detecting unit detects an instruction address at the time of generation of an interrupt signal from a timer, and a calculating unit calculates a variation amount of a counted value by a hardware counter at a detected instruction address. The variation amount is accumulatively retained for each detected instruction address. A specifying unit specifies an instruction address that corresponds to the event, and a display unit displays a graph of the total variation amounts.

Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.

Abstract: A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.