Abstract: A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred.

Abstract: Provided is an ion implantation apparatus including a disk which rotates about a first axis, a pad which is rotatable about a second axis on the disk, and on which a substrate is placed with a holder attached to a circumference of the substrate, the holder including a weight, fixing pins which are each fixedly provided on a portion on the disk around the pad, a sliding piece which slides, by its own centrifugal force, on the disk with a rotational movement of the disk and thereby clamps the holder in cooperation with the fixing pins, and an ion beam generator which irradiates the substrate with ion beams.

Abstract: An information processor for controlling a storage device for storing content information, includes: a controller for receiving content information from the exterior and storing the content information in the storage device; and a generator for generating unique information that is unique to combination of the content information and the information processor through an operation of identification information of the content information and the information processor; wherein when the controller receives content information, the controller checks whether the content information includes information matching with the unique information and upon confirmation of both the information allows the content information to be stored in the storage device.

Abstract: A RAID controller selecting a plurality of storages forming RAID includes a data input part having a plurality of data input terminals; a control signal input part having a control signal input terminal to which a control signal related to path setting is inputted; a data output part having a plurality of data output terminals; and a path selection part connecting a data input terminal selected from among the plurality of data input terminals with a data output terminal selected from among the plurality of data output terminals based on the control signal when the control signal is inputted to the control signal input terminal.

Abstract: A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film.

Abstract: A method of performing an optical proximity effect correction to a first photomask pattern for a wiring of a semiconductor device for use in combination with a second photomask pattern for a via, the wiring including an end portion coupled to the via, the method being performed by a computer including a memory storing layout data of the first photomask pattern and the second photomask pattern, including extracting a pattern of layout data of the first photomask pattern for the wiring corresponding to the end portion of the wiring and layout data of the second photomask pattern for the via.

Abstract: An output voltage controller includes a first controller which controls current supply to a inductor based on an output voltage, and a second controller which controls current supply to the inductor by controlling a period when an input end to which an input voltage is inputted, the inductor, and an output end from which the output voltage is outputted are coupled based on the input voltage.

Abstract: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.

Abstract: A semiconductor device includes a plurality of chips comprising a plurality of first moisture-proof rings individually surrounding said plurality of chips, a second moisture-proof ring surrounding the entire plurality of chips, and a wire for connecting said plurality of chips to each other.

Abstract: A stacked film of a first insulation film being a silicon oxide film with an extremely low moisture content, and a second insulation film being a silicon oxide film with a higher moisture content than the first insulation film, therefore, with a low in-plane film thickness distribution rate is formed, and this is polished by CMP. Polishing is performed until the second insulation film is wholly removed directly above a ferroelectric capacitor structure and a surface of the first insulation film is exposed to some extent. At this time, surface flattening is performed for a top surface of a first portion in the first insulation film and a top surface of the second insulation film, and an interlayer insulation film constituted of the first insulation film and the second insulation film remaining on a second portion of the first insulation film is formed.

Abstract: It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.

Abstract: A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.

Abstract: A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line.

Abstract: A defect review apparatus includes a storage device which stores data about a defect of an inspection target object; a first imaging device which captures an image located in a position on a surface of the inspection target object, the position being specified by information regarding the position of the inspection target object which has been input; and a control device which controls the first imaging device. The storage device stores: first defect detection data including a defect number as which the defect of the inspection target object detected by a first defect detection process is labeled, and information regarding the position of the defect; and second defect data including a defect number as which the defect of the inspection target object detected by a second defect detection process is labeled, and information regarding its position.

Abstract: A control circuit for a DC-DC converter includes a controller configured to control, based on a feedback voltage, a first switch provided between an inductor and a reference potential and a second switch provided between a coupling node of the first switch and the inductor and an output terminal, a third switch provided between the second switch and the output terminal and turned off when an overcurrent flows in a coupling path between the second switch and the output terminal, and a selector configured to select a voltage of a first position which is located on a side of the second switch in the coupling path as the feedback voltage when the third switch is turned off, or a voltage of a second position which is located on a side of the output terminal in the coupling path as the feedback voltage when the third switch is turned on.

Abstract: A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.

Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.