Abstract: A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a testing device is connectable to the terminal. The input/output cell has a switching part that is capable of switching between a first path that loops back at an output side of the output-stage buffer and a second path that loops back at an input side of the output-stage buffer. The first path is selected during normal operation and the second path is selected during the propagation delay testing.

Abstract: A manufacturing method of an electronic device, includes the steps of: implanting P (phosphorous) ions into a substrate semiconductor region made of Si or SiGe by using a resist as a mask; ashing the resist while it is heated in a vacuum environment; and taking out the substrate, the substrate being ashing processed so that a temperature of the substrate is equal to or less than 130° C.

Abstract: Abnormal values of an objective variable are removed. A degree of association between an objective variable and a plurality of explanatory variables is calculated. A plurality of explanatory variables having a high degree of association are extracted. A degree of independence between the explanatory variables is calculated. A plurality of candidates of explanatory variables with a high possibility of having a great effect on the objective variable are selected based on the degree of association and the degree of independence. An explanatory variable having a high rate of contribution to the objective variable is selected from among the candidates, based on the cumulative contribution rate, and a regression equation is calculated to estimate a value of the objective variable. The same processing is repeated, using the difference as a new objective variable and explanatory variables except the explanatory variable used to obtain the difference as new explanatory variables.

Abstract: There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device isolation trench. At least a surface part of the device isolation insulation film is formed of an HF-resistant film.

Abstract: An electronic device provided with a system main unit including a load powered by operational voltage. A system power supply unit, connected to the system main unit, supplies the load with the operational voltage. The system main unit includes a memory circuit for storing initial value data containing a set value for setting the operational voltage of the load. A main unit communication circuit reads the initial value data from the memory circuit and transmits the initial value data to the system power supply unit. The system power supply unit includes a power supply communication circuit for communicating with the main unit communication circuit to receive the initial value data. A voltage generation circuit generates voltage corresponding to the set value.

Abstract: A method of inspecting defects on an object includes irradiating predetermined particles with a laser beam to measure first scattered light intensities, irradiating plural types of defects with the laser beam to measure second scattered light intensities, determining types of some defects selected out of the plural types of defects using the first scattered light intensities, setting a discrimination line indicating a boundary value of the second scattered light intensities based on the determination, and discriminating, using the discrimination line, defects on the object.

Abstract: A power supply system including an external power supply unit generating direct-current output voltage and an electronic device connected to the external power supply unit and operable on the output voltage of the external power supply unit. The external power supply unit includes a voltage control circuit receiving control current and controlling the output voltage of the external power supply unit in accordance with the control current. The voltage control circuit controls the output voltage of the external power supply unit to be equal to the minimum voltage possible for the external power supply unit to generate when the control current is minimum.

Abstract: There is provided a method of manufacturing a mask for exposure, which is capable of measuring the phase difference between a shifter portion and a non-shifter portion with good accuracy. A mask for exposure having: two first light-shielding device patterns, which are formed on a quartz substrate (transparent substrate) in a device region at a first gap and extend over a first concave portion; a second device light-shielding pattern at a second gap from the first device light-shielding pattern; two first light-shielding monitor patterns, which are formed on the quartz substrate in a monitor region at a third gap wider than the first gap and extend over a second concave portion; and second light-shielding monitor pattern, which has a fourth gap wider than the second gap from the first light-shielding monitor pattern, in which the size of the first light-shielding monitor pattern is equal to or less than the size of the first light-shielding device pattern.

Abstract: A semiconductor device includes a pad, an internal power supply line, a pad switch including a MOS transistor to provide an electrically connectable coupling between the internal power supply line and the pad by use of a source-drain channel thereof, and a control circuit configured to control an electrical connection with respect to at least one of a gate node and a back-gate node of the MOS transistor, wherein the control circuit is configured such that at least one of the gate node and the back-gate node is electrically connectable to the pad.

Abstract: To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugs 32a, 32b in first and second holes 11a, 11b in a first insulating film 11; a step of forming a first opening 14a in an oxidation preventing insulating film 14; a step of forming an auxiliary conductive plug 36a in the first opening 14a; a step of forming a capacitor Q on the auxiliary conductive plug 36a; a step of forming third and fourth holes 41a, 41b in a second insulating film 41 covering the capacitor Q; a step of forming the second opening 14b in the oxidation preventing insulating film 14 under the fourth hole 41b; a step of forming a third conductive plug 47a in the third hole 41a; and a step of forming a fourth conductive plug 47b in the third hole 41a.

Abstract: To provide a high-performance, highly-reliable semiconductor device in which an adhesive used to mount (e.g., flip-chip mount) a semiconductor chip on a substrate has less air bubbles, and a low-cost, efficient method for manufacturing the same. Semiconductor device 10 of the present invention includes semiconductor chip 11 having a plurality of electrode pads 12, and substrate 14 having a plurality of electrode terminals 15 at positions corresponding to electrode pads 12. A plurality of bumps 13, each composed of base part 13A and protruding part 13B having a diameter smaller than the diameter of base part 13A, is formed on at least one of electrode pads 12 in such a way that the respective base parts 13A of bumps 13 are in contact with each other, and semiconductor chip 11 is bonded to substrate 14 with adhesive 17 in a state where bumps 13 are electrically connected to electrode terminals 15.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: A processor includes an execution unit configured to execute a program, a bus coupled to the execution unit, a local memory coupled to the bus, a DMA unit coupled to the bus, and an interface to couple the bus to an exterior, wherein the DMA unit is configured to perform a DMA transfer process in response to instruction from the execution unit, to load information by the DMA transfer process from the exterior through the interface, to decrypt the loaded information, and to write the decrypted information to the local memory by the DMA transfer process.

Abstract: A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Abstract: An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove 11 just above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring groove 11A in a position spaced away from just above the hole is exposed to the light.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract: The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region on both sides of the gate electrode, and which constitutes a MOS transistor of an SRAM memory cell with the gate electrode, an interlayer insulating film formed over each of the active region and the device isolation insulating film, a first hole which is formed in the interlayer isolation insulating film, and which commonly overlaps with two adjacent active regions and the device isolation insulating film between the active regions, and a first conductive plug which is formed in the first hole, and which electrically connects the two active regions.

Abstract: A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis(tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.

Abstract: A multiphase clock generator circuit for generating a plurality of output clock pulses that differ in phase on the basis of a reference clock pulse, has first and second divider circuits for dividing first and second reference clock pulses that differ in phase to generate output clock pulses, and a switch for forming an intermittent short between predetermined nodes of the first and second divider circuits, wherein the switch forms a short between the predetermined nodes with timing in which the predetermined nodes are brought to the same level in a normal operating state.