Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material. a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors.

Abstract: A delay clock generator includes a plurality of delay element arrays arranged in parallel; a feed side transfer line and a return side transfer line provided in each of the delay elements which make up the delay element arrays, and that transfer a clock signal in a feed direction and a return direction; a selector selecting a first transfer route that couples the feed side transfer lines to each other along the preceding and succeeding delay elements and a third transfer route that couples the return side transfer lines to each other along the preceding and succeeding delay elements, and a second transfer route that couples the feed side transfer lines and the return side transfer lines of each of the delay elements; and a decoder causing the selector to select the second transfer route for one of the delay elements in the delay element array.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.

Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Abstract: A carrier interpolation unit (a digital filter) performs interpolation processing of SP signal in the frequency domain. An IFFT circuit converts a frequency-domain signal into a time-domain signal. A delay profile generation unit generates a delay profile based on an output of the IFFT circuit. The filter control unit controls a pass band of the digital filter in accordance with the delay profile. An FFT window control unit controls a position of a window to extract a calculation range of FFT in accordance with the delay profile. When delay time of multipath is larger than the guard interval, and when the reception power of the interference wave is larger than a threshold, the pass band of the digital filter is minimized.

Abstract: Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.

Abstract: Exposure verification is applied to exposure data indicating a pattern to be exposed by a charged particle beam. If an error point is extracted from the exposure data by the exposure verification, the values of coefficients are modified and exposure data is regenerated taking into consideration the coefficients whose values have been modified. Thus, exposure data is re-generated by changing each of the coefficient values within its appropriate range.

Abstract: An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERA1G has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VV1 provided from a first voltage divider circuit VD1 is fed into the inverting input; a reference voltage e1G from ground is fed into the first non-inverting input; and a second divided voltage VV2 provided from a second voltage divider circuit VD2 is fed into the second non-inverting input. The error amplifier ERA1G amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e.

Abstract: An image processing apparatus for correcting image distortion includes a storage which stores before-correction coordinates in a coordinate system of a before-correction image, corresponding to each pixel in a coordinate system of a corrected image; a coordinate output section which reads from the storage and outputs the before-correction coordinates corresponding to coordinates input to select each pixel of the corrected image; a pixel data output section which outputs the data of the before-correction image, corresponding to the before-correction coordinates, as the data of the pixel of the corrected image, corresponding to the before-correction coordinates; and a pixel data calculator which calculates, when the before-correction coordinates include a value after the decimal point, a weighted average based on the data of a plurality of pixels close to the before-correction coordinates in the before-correction image to output the weighted average as the data of the pixel of the corrected image.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.

Abstract: A semiconductor device includes non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. The semiconductor device has memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate (1) having first and second areas (AR1, AR2), a floating gate structure (4, 5, 6, 7, 8) for a non-volatile memory cell, a control gate structure (14) formed coupled to the floating gate structure, formed in the first area, and an insulated gate electrode (12, 14) for a logical circuit formed in the second area, wherein the floating gate structure has bird's beaks larger than those of the insulated gate electrode.

Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A feature amount of an inter-mobile unit relative movement are detected as an observation amount by an observation amount detecting section 26, time series of the observation amounts are stored as an observation series into a storage section 27 to calculate a similarity of the observation series to a predetermined collision observation series by a classification section 28. A determination section 29 determines to be a collision accident if, in a case where the similarity is larger than a predetermined value, a mobile unit associated with the similarity is at rest in a stoppage prohibition area set in a storage section 30 and another mobile unit is moving, and to be a mobile unit failure if collision determination conditions except for the similarity are met.