SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD
A semiconductor device includes non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. The semiconductor device has memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate (1) having first and second areas (AR1, AR2), a floating gate structure (4, 5, 6, 7, 8) for a non-volatile memory cell, a control gate structure (14) formed coupled to the floating gate structure, formed in the first area, and an insulated gate electrode (12, 14) for a logical circuit formed in the second area, wherein the floating gate structure has bird's beaks larger than those of the insulated gate electrode.
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This application is a divisional application of U.S. Ser. No. 11/145,214 filed Jun. 6, 2005, which is a continuation of PCT/JP2003/003382 filed on Mar. 19, 2003, the entire contents of which being incorporated herein by reference.
BACKGROUND OF THE INVENTIONA) Field of the Invention
The present invention relates to a semiconductor device, and its manufacture method, and more particularly to a semiconductor device having a memory circuit of, for example, non-volatile memory cell transistors and a peripheral circuit of logical cell transistors, and to its manufacture method.
B) Description of the Related Art
Known as the structure of an electrically erasable non-volatile memory, is a structure having a lamination of a floating gate structure having a charge retention function and a control gate structure for applying an electric field to a channel via the floating gate structure, stacked on a semiconductor region formed with the channel. The floating gate structure includes a silicon layer insulated with an insulating layer or layers, or a lamination of an oxide film, a nitride film and an oxide film, forming a nitride film interface having a charge storage function.
Programming (data write) is performed by selectively injecting electrons into the floating gate. When a predetermined voltage is applied to the control gate structure, the conductivity of a channel below the floating gate changes, depending on whether or not there are charges in the floating gate structure. Hence, written information can be read. By draining electrons from the floating gate structure, written information can be erased.
It is preferable to cover the side walls of the floating gate structure with an insulating film of good quality, in order to reduce leak of charges written in the floating gate structure. For example, a floating electrode is formed by a silicon layer sandwiched between insulating layers, and side walls are thermally oxidized. A floating gate electrode covered with an insulating film of good quality such as a thermally oxidized film improves the charge retention performance. The charge retention performance of a floating gate structure made of a lamination of oxide film-nitride film-oxide film can also be improved by covering the side walls with an oxide film or the like.
A semiconductor integrated circuit such as a system LSI of high integration degree is structured having a plurality type of semiconductor elements such as non-volatile memories, high voltage insulated gate field effect (abbreviated to MOS) transistors for driving them and low voltage MOS transistors for logical circuits. A logical circuit low voltage MOS transistor has a short gate length and a thin gate insulating film in order to raise its operation speed.
Manufacture processes for a semiconductor integrated circuit are designed to use in common as many same processes as possible for the manufacture of a plurality type of semiconductor elements. For example, the gate electrode of a MOS transistor is made of the same silicon layer as that of the control gate electrode of a non-volatile memory cell.
In the process of thermally oxidizing the side walls of a floating gate electrode, the side walls of the gate electrode of a MOS transistor are also thermally oxidized. During the thermally oxidizing process, oxidizing species enter the interface between a silicon substrate and an upper insulating film and the interface between a silicon layer and an insulating film so that an oxidized region called a bird's beak is formed.
A low voltage MOS transistor has a short gate length and a thin gate insulating film. As a birds' beak is formed at the edge portions of a gate insulating film, the gate insulating film becomes thick under the edge portions of the gate electrode so that a drive current of the MOS transistor is lowered.
A laminated gate structure of a non-volatile memory cell and a single layer gate structure of a MOS transistor are patterned by using different masks and different processes. Therefore, mask alignment margins are increased. If a first mask alignment margin is 0.2 μm, a second mask alignment margin is increased to 0.28 μm. An increase in the mask alignment margin hinders high integration.
Japanese Patent Laid-open Publication No. HEI-10-223782 proposes a non-volatile memory cell whose control gate electrode is made of a diffusion region in a substrate. A low resistance region functioning as a control gate electrode is formed in a semiconductor substrate, and a floating gate electrode is formed extending from an area above a channel region of the memory transistor to an area above the low resistance region functioning as the control gate electrode. The control gate electrode can be formed by the same process as that for the source/drain regions of the memory transistor, so that the manufacture processes for a non-volatile memory can be simplified.
SUMMARY OF THE INVENTIONAn object of the present invention is to provide a semiconductor device having memory cells with a high data retention ability and field effect transistors having an insulating film realizing a high drive current.
Another object of the present invention is to provide a semiconductor device capable of enhancing a data retention ability of a non-volatile memory cell and preventing lowering of the drive current of a field effect transistor having an insulated gate in a logical circuit.
Another object of the present invention is to provide a method of manufacturing the semiconductor device as described above.
Another object of the present invention is to provide a method of manufacturing at a high precision the semiconductor device as described above.
Still another object of the present invention is to provide a method of manufacturing efficiently the semiconductor device as described above.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first element area and a second element area on a surface thereof; a first transistor of a double gate type having a floating gate and a control gate whose side walls are covered with a thermally oxidized film, and having gate bird's beaks having a first length, formed in the first element area; and a second transistor having a gate electrode having gate bird's beaks having a second length shorter than the first length, formed in the second element area, wherein the first transistor operates as a non-volatile memory cell capable of electrically writing and erasing data and the second transistor operates as a logical circuit element.
According to another aspect of the present invention, there is provided a manufacture method for a semiconductor device, comprising steps of: (a) forming an element separation region in a semiconductor substrate to define first and second areas; (b) forming a floating gate structure lamination layer on the first area; (c) forming a lamination of a gate electrode conductive layer and a masking insulating layer above the floating gate structure lamination layer and above the second area; (d) pattering the masking insulating film in a gate electrode shape; (e) masking the second area, and by using the masking insulating layer as an etching mask, etching the gate electrode conductive layer and the floating gate structure lamination layer in the first area to pattern a floating gate structure and a control gate structure; (f) forming an oxide film on side walls of at least the floating gate structure; and (g) masking the first area, and by using the masking insulating layer as an etching mask, etching the gate electrode conductive layer in the second area to pattern an insulated gate structure.
Embodiments of the present invention will be described with reference to the accompanying drawings.
An electrically erasable non-volatile semiconductor memory uses high voltage for programming and erasure. If a programming circuit and an erase circuit are integrated with a non-volatile memory circuit, high voltage field effect (abbreviated to MOS) transistors are required to be integrated. A logical circuit is made of low voltage MOS transistors for reducing the power dissipation. If a non-volatile memory circuit and a logical circuit are integrated, low voltage MOS transistors are required to be integrated.
First EmbodimentAs shown in
A thermally oxidized film 4 is formed to a thickness of 6 nm to 12 nm in an oxidizing atmosphere by heating the semiconductor substrate to 800° C. to 1100° C. This thermally oxidized film 4 constitutes a tunneling oxide film of a non-volatile memory cell.
As shown in
On the amorphous silicon film 5, a silicon oxide film 6 having a thickness of 4 nm to 8 nm is formed by CVD at a temperature of 700° C. to 800° C. and a silicon nitride film 7 having a thickness of 5 nm to 10 nm is formed by CVD at a temperature of 650° C. to 800° C. A thermally oxidized film 8 having a thickness of 3 nm to 10 nm is formed on the surface of the silicon nitride film 7 in an oxidizing atmosphere at 900° C. to 1000° C. The above-described and subsequent heating processes change the amorphous silicon film to a polysilicon film. In this manner, a lamination of an oxide film—a nitride film—an oxide film (ONO film) is formed on the silicon film 5.
As shown in
As shown in
In this manner, a thin gate oxide film 12 suitable for the low voltage MOS transistor is formed in the area AR2 and a thick oxide film 11 suitable for the high voltage MOS transistor is formed in the area AR3.
As shown in
If low resistance is desired, a tungsten silicide (WSi) film may be grown on the amorphous silicon film by CVD to a thickness of 100 nm to 200 nm.
A plasma-enhanced CVD nitride film 15 as a hard mask layer is grown to a thickness of 20 nm to 150 nm. In place of the plasma-enhanced CVD nitride film, a hard mask layer of a plasma-enhanced CVD oxynitride film, a plasma-enhanced CVD oxide film or the like may be used. Formed in this manner is a lamination of a conductive layer as a gate electrode and an upper hard mask layer. On the hard mask layer 15, a resist pattern 16 having each gate electrode shape is formed.
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In the areas AR2 and AR3, an oxide film 18 is formed on the surface of the silicon layer 14. Since the surface of the silicon substrate 1 is covered with the gate oxide films 11 and 12 and silicon film 14, it is not oxidized.
As shown in
A high impurity concentration n-type region 22 is formed by implanting arsenic ions at an acceleration energy of 30 keV to 60 keV and a dose of 2×1015 cm−2 to 7×1015 cm−2. In this manner, the high impurity concentration source/drain regions 22 are formed on both sides of the gate electrode and the low impurity concentration n-type region 21 is formed surrounding at least one of the source/drain regions 22. The low impurity concentration n-type region 21 exhibits the function of raising an efficiency of draining charges from the silicon layer 5.
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In the manner described above, non-volatile memory cells are formed in the area AR1, low voltage MOS transistors are formed in the area AR2, and high voltage MOS transistors are formed in the area AR3. High drive performance of MOS transistors is retained because bird's beaks are prevented from being formed. A position alignment margin is small since the gate electrode of each semiconductor device is formed by a single mask process.
In the gate electrode of a MOS transistor, the silicon gate electrode 14 is formed on the gate oxide film 12 (11) of uniform thickness. Since no bird's beak is formed at the gate oxide film 12 (11), a voltage applied to the gate electrode is efficiently applied to the channel so that the drive performance of the MOS transistor can be retained. There may be some possibility of allowing generation of weak bird's beaks under the gate electrode of logical MOS transistor, such bird's beaks are shorter than the bird's beaks of the non-volatile memory cell, and will not appreciably affect the performance of the logical MOS transistor.
In the embodiment described above, the thermally oxidized film is formed on the side walls of the floating gate electrode of a non-volatile memory cell and bird's beaks are allowed to be formed. No bird's beak is formed in the low voltage MOS transistor and high voltage MOS transistor.
The operation of a high voltage MOS transistor is not hindered by bird's beaks at the edge portions of a gate electrode, and bird's beaks provide a function of raising a breakdown voltage.
Second EmbodimentAs shown in
As shown in
Thereafter, processes similar to those described with
In the first and second embodiments, the floating gate structure is made of a silicon layer. The floating gate structure with the charge retention function may also be made of an ONO film.
Third EmbodimentAs shown in
The area AR1 is covered with a resist pattern 9. By using the resist pattern 9 as an etching mask, the ONO film 6, 7, 8 in the areas AR2 and AR3 is etched. The resist mask 9 is thereafter removed.
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A resist pattern 16 having each gate electrode shape is formed on the hard mask layer 15. By using the resist pattern 16 as an etching mask, the hard mask layer 15 is patterned in the gate electrode shape. Thereafter, a process similar to the process shown in
As shown in
Processes similar to those shown in
In the third embodiment, no bird's beak is formed under the gate electrode of the high voltage MOS transistor. Similar to the second embodiment, bird's beaks may be formed under the gate electrode of the high voltage MOS transistor.
Fourth EmbodimentAs shown in
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Thereafter, similar to the process shown in
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Thereafter, processes similar to those shown in
Referring to
As shown in
A hard mask layer 15 such as silicon nitride is formed on the silicon layer 41, and a resist pattern 16 having each gate electrode shape is formed on the hard mask layer. This state corresponds to the state shown in
By using the resist pattern 16 as an etching mask, the hard mask 15 is etched. The resist pattern 16 is thereafter removed.
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Thereafter, in the areas AR2 and AR3, high impurity concentration source/drain regions are formed.
As show in
Bird's beaks may be formed under the gate electrodes of the high voltage MOS transistor.
Sixth EmbodimentFirst, as shown in
As shown in
Thereafter, by covering the areas AR2 and AR3 with a resist mask, ion implantation is performed for non-volatile memory cells.
As shown in
Thereafter, by covering the area AR1 with a resist mask, ion implantation is performed for extension regions of source/drain regions in the areas AR2 and AR3.
As shown in
In this embodiment, bird's beaks are formed under the gate electrode of high voltage MOS transistor to improve the breakdown voltage of the gate electrodes. Other points are similar to the fifth embodiment.
The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. For example, various kinds of insulators may be used as the material of the hard mask layer. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.
It is possible to manufacture a semiconductor device such as a system LSI including non-volatile memory cells and other types of semiconductor elements.
Claims
1. A semiconductor device comprising:
- a semiconductor substrate having on a surface thereof a first element area, a second element area, and a third element area separated by shallow trench isolation;
- a first transistor having a first gate structure in said first element area, side walls of said first gate structure being covered with a first thermally oxidized film;
- a second transistor having a second gate structure in said second element area, and having no bird's beak; and
- a third transistor having a third gate structure in said third element area, side walls of said third gate structure being covered with a second thermally oxidized film, and having thermally oxidized gate bird's beaks under edge region of the third gate structure;
- wherein said first transistor operates as a non-volatile memory cell, said second transistor operates as a low voltage logical circuit element, and said third transistor operates as a high voltage logical circuit element.
2. The semiconductor device according to claim 1, wherein said first gate structure includes a first gate insulating film formed above said first area and including thermally oxidized gate bird's beaks under edge regions of the first gate structure, a floating gate formed of a first silicon layer formed on said first gate insulating film, a second gate insulating film formed on said first silicon layer and a control gate formed of a second silicon layer formed on said second gate insulating film.
3. The semiconductor device according to claim 2, wherein said second gate insulating film includes an insulating lamination of an oxide film, a nitride film and an oxide film.
4. A semiconductor device comprising:
- a semiconductor substrate having on a surface thereof a first element area, a second element area, and a third element area, separated by shallow trench isolation;
- a first transistor having a first gate structure in said first element area, side walls of said first gate structure being covered with a thermally oxidized film, and said thermally oxidized film and said first gate structure being covered with a deposited oxide film;
- a second transistor having a second gate structure in said second element area, side walls of said second gate structure being covered with said deposited oxide film, but top surface of said second gate structure being not covered with said deposited oxide film, and said second gate structure having no gate bird's beak,
- a third transistor having a third gate structure in said third element area, side walls of said third gate structure being covered with said deposited oxide film, but top surface of said third gate structure being not covered with said deposited oxide film,
- wherein said first transistor operates as a non-volatile memory cell, said second transistor operates as a low voltage logical circuit element, and said third transistor operates as a high voltage logical circuit element.
5. The semiconductor device according to claim 4, wherein said first gate structure includes a gate insulating film formed above said first element area and including thermally oxidized gate bird's beaks under edge portions of the first gate structure.
Type: Application
Filed: Dec 17, 2009
Publication Date: Apr 22, 2010
Applicant: FUJITSU MICROELECTRONICS LIMITED (Tokyo)
Inventors: Hiroshi HASHIMOTO (Kawasaki), Kazuhiko TAKADA (Kawasaki)
Application Number: 12/640,067
International Classification: H01L 29/788 (20060101); H01L 29/78 (20060101);