Abstract: A switch device includes a semiconductor chip, and at least two switches formed on the semiconductor chip. Ground parts of the at least two switches are arranged between said at least two switches.

Abstract: A device includes a transistor, and two interdigital capacitors. The transistor is located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.

Abstract: A high-frequency input impedance matching circuit includes an inductor connected between an input of a transistor and an input terminal of the high-frequency input impedance matching circuit, a first capacitor having one end connected to the input terminal and another end connected to a ground, and a second capacitor connected to the inductor in parallel.

Abstract: A semiconductor integrated circuit device includes a semiconductor layer on a substrate, a first gate electrode formed on the semiconductor layer, and a second gate electrode that is formed on the semiconductor layer and is adjacent to a sidewall of the first gate electrode along a channel length. The first and second gate electrodes have different work functions.

Abstract: A negative resistance circuit having an output terminal is connected to a first terminal of a strip shaped resonator. Anode of a variable capacitance diode is connected to a second terminal of the strip shaped resonator via a capacitor 1′. Cathode of the variable capacitance diode is grounded. One terminal of a high impedance strip shaped line is connected to the anode of the variable capacitance diode. Other terminal of the strip shaped line is grounded via a capacitor 4. The capacitor 4 has sufficiently low impedance at an oscillation frequency.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a mask on a predetermined layer, said mask having a first opening at a given side of the predetermined layer and a second opening that continues to and is smaller than the first opening, and forming a plating layer on the predetermined layer by using the mask.

Abstract: A compound semiconductor device includes a cap layer formed on a channel layer and an insulating film formed on the cap layer, and a &Ggr;-shaped gate electrode is provided in a gate recess opening, wherein an extension part of the &Ggr;-shaped gate electrode extends over the insulating film toward a drain electrode, and the total thickness of the insulating film and the cap layer being is set such that the electric field formed right underneath the extension part of the gate electrode includes a component acting in a direction perpendicular to the substrate.

Abstract: A high frequency semiconductor device includes semiconductor elements provided on a semiconductor substrate, a surface insulating layer for covering the semiconductor elements, at least one wiring layer which is provided above the surface insulating layer, with at least one insulating interlayer provided therebetween, and which combines with the ground potential to form transmission line, and at least one heat-radiating stud which is provided in at least one throughhole so as to penetrate said insulating interlayers and so as not to penetrate said surface insulating layer.

Abstract: An optical semiconductor element and an optical element having an optical coupling facet are disposed on a support surface of a platform. The optical element is optically coupled to the optical semiconductor element at the optical coupling facet. A protective member covers the optical semiconductor element and is disposed at least in a light transmission area in a space between the semiconductor element and the optical coupling facet of the optical element. The protective member is made of gel acrylic modification resin. An optical semiconductor module having a sufficient moisture resistance and being suitable for low cost is provided.

Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

Abstract: At least a channel layer and an etching stopper layer are provided on a semiconductor substrate in order, a gate electrode that Schottky-contacts the etching stopper layer is provided on the etching stopper layer, and InGaP having an In composition ratio of 0.66 through 0.9 is used as the etching stopper layer in a field effect type compound semiconductor device.

Abstract: In the high frequency amplifier bias circuit, an emitter-follower-transistor, which serves to supply a bias electric current corresponding to a control input voltage input from outside, is connected to a base of the transistor for amplification. The transistor for current control is connected in series to emitter of the transistor for bias supply, and bypasses electric current corresponding to the control input voltage. Electric current corresponding to the control input voltage flows through the first transistor for temperature compensation. Electric current corresponding to electric current flowing through the first transistor for temperature compensation flows through the transistor for current control.

Abstract: The capacitor comprises: a lower electrode 12 formed on a substrate 10; an insulation film 16 having an opening 24 on the lower electrode 12; a capacitor dielectric film 30 formed on the lower electrode 12 in the opening 24 and having a larger thickness at a peripheral part of the opening 24 than at a central part of the opening; and an upper electrode 32 formed on the capacitor dielectric film 30. Thus, degradation of the breakdown voltage and stress resistance of the peripheral part of the opening 24, which is due to the coverage of the capacitor dielectric film, can be suppressed.

Abstract: An S3-type laser diode includes a p-type cladding layer formed on an active layer such that an inclined surface region thereof has a carrier concentration level of 1×1018 cm−3 or more, wherein the p-type cladding layer has a thickness of 0.35 &mgr;m or more.

Abstract: An optical device includes a rigid pipe provided to cover the outer peripheries of a fixing joint portion and an optical fiber. The tip portion of the rigid pipe has a gap for providing flexibility between the optical fiber and the tip portion. Therefore, the rigid pipe suppresses bending of the optical fiber to avoid concentration of stress in the fixing joint portion for fixing the optical fiber to an optical unit section, thereby avoiding breakage of the optical fiber in the fixing joint portion.

Abstract: A semiconductor device includes a SAW device chip. The SAW device chip is provided on a passive element chip in which a passive element circuit including a transmission line is formed on a semi-insulating compound substrate having one surface set to have a ground potential electrode. In the semiconductor device, even when the width of the transmission line is increased, a high characteristic impedance can be maintained by increasing the thickness of the substrate. This can reduce the resistance of the transmission line and can facilitate matching with the SAW device.

Abstract: A high-frequency module includes a substrate including a thin film resin sheet. A high-frequency circuit wiring line forming a first wiring layer is formed and a high-frequency circuit component is provided on an upper surface of the substrate. A resin sealing package seals the first wiring layer and the high-frequency circuit component.

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract: There is provided a semiconductor laser which comprises a first cladding layer formed of compound semiconductor having first conductivity type impurity and having a mesa-shaped projection, an active layer formed on the projection like a stripe and having side surfaces which are inclined at an angle of more than 70 degrees but less than 90 degrees relative to an upper surface of the first cladding layer, buried layers formed on both sides of the projection and having second conductivity type impurity, current blocking layers each having one end which contacts a virtual surface obtained by extending upward a side surface of the active layer and having a first facet which extends downward from the one end and is inclined by about 55 degrees relative to the upper surface of the first cladding layer and formed on each buried layer and having the first conductivity type impurity, and second cladding layers formed on the current blocking layers and the active layer and having the second conductivity type impurity.

Abstract: An n type InP buried layer 22 with Se or S added in an above 5×1018 cm−3 concentration is formed on an active layer mesa stripe 18 having a surface with an SiO2 film 16 formed on at a peripheral part of the mesa stripe 18 other than the surface with the SiO2 film 16 formed on. Accordingly, the buried layer can be grown without the over growth.