Abstract: A method of manufacturing a semiconductor device having an insulated gate type field effect transistor. A gate insulating film, a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed therebetween, an interlayer insulating film, and a wiring layer connected to the gate electrode layer, are formed on a semiconductor substrate in the order recited. A conductive material layer and a resist layer are formed on the wiring layer. The resist layer is patterned to form a resist mask forming a wiring pattern having an antenna ratio of about ten times or more of the predetermined area of the gate electrode layer. At least the conductive material layer is plasma-etched by using the resist mask as an etching mask, and thereafter, the resist mask is removed and the wiring layer is plasma-etched.

Abstract: An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution.

Abstract: An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution.

Abstract: An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.

Abstract: The present invention provides an A/D converter. An upper comparison voltage generator divides a reference voltage into a plurality of large-level regions with series-connected first voltage-dividing elements, and outputs voltages at boundaries of the individual large-level regions as upper comparison voltages. Upper comparators compare an analog input voltage with the individual upper comparison voltages. An upper encoder determines, from output signals of the upper comparators, to which one of the large-level regions the analog input voltage belongs, and outputs a predetermined upper digital code corresponding to the determined large-level region. A lower comparison voltage generator divides the large-level region to which the analog input voltage is determined to belong by the upper encoder, into a plurality of small-level regions with second voltage-dividing elements and outputs voltages at boundaries of the individual small-level regions as lower comparison voltages.

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L<(2Edt.sup.3 /3P).sup.1/4, wherein E is a Young's modulus of a material of the first member; d is a distance of the space between the first member and the rigid component; t is a thickness of the first member; and P is an external pressure applied to the first member; or b) for the first member adjacent to the second member: L<(2Ed't.sup.3 /3P).sup.1/4, wherein E, t and P are as defined above; and d' is a distance of the space between the first and second members.

Abstract: A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A small computer system interface device is capable of transmitting data between a central digital data processing device and an external device without the need for terminal resistors coupled between the SCSI and the central digital data processing device. A pair of data buses each containing equal number of data lines supply data to a protocol controller which identifies the number of data lines being used to transfer data and then transfers the supplied data to a disk drive unit using the full number of data lines provided by said pair of buses. When the number of bus lines used is less than that provided by both buses, the protocol controller signals a level setting circuit to set the number of bus lines unused by to transfer data from the central digital processing device inactive so as to allow the throughput of data between the digital processing device, SCSI and disk drive unit.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A data processor including a data control unit having a computing portion, including a first storage unit for writing and reading a first set of data for supporting the computing portion, a second storage unit for writing and reading a second set of data for supporting the computing portion, and an arithmetic unit for calculating the first set of data read out of the first storage unit and the second set of data read out of the second storage unit and outputting result data.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: A system and method is presented for generating a computer assisted design circuit net list descriptive of a semiconductor integrated circuit design based on mask patterns used during the formation of the semiconductor. Masking pattern data, stored in a library data base, is processed by a central processing unit into primitive elemental circuit data and interconnection data. Coordinate and other information included in the primitive and interconnection data is then simplified. The simplified data is then supplemented to account for data simplification. The supplemented data is further processed to generate a symbolic circuit layout and a primitive net list.