Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption.

Abstract: A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source.

Abstract: A delay time computing apparatus includes a data base for storing data on various cells, an input device operable by a designer, and a processing unit coupled to the data base and the input device. The processing unit includes a data input interface, a path building section and a delay time computing section. The data input interface controls transfer of input data from the input device. The path building section reads detailed data on a selected cell from the data base in accordance with circuit redesign data input by a circuit designer to the data input device, and thereby constructs a signal propagation path for cells involved in circuit redesign. Every time the path building section constructs new signal propagation paths, the delay time computing section computes delay times of cells involved in circuit redesign.

Abstract: A method is disclosed, which sequentially inspects a plurality of semiconductor devices formed on a semiconductor wafer. This method executes a full inspection analysis on the individual devices on the wafer. The full inspection is carried out based on predetermined inspection criteria to determine whether or not the inspected devices are defective or properly functional. The number of devices determined as good ones during the full inspection analysis is sequentially counted, whereas the counted number is reset to zero whenever any device is determined to be defective during the full inspection routine. A simplified inspection analysis is executed on a predetermined number of devices when the counted number reaches a predetermined value. The simplified inspection is carried out against some of all the predetermined inspection criteria to determine whether or not the inspected devices are defects.

Abstract: A method is disclosed to execute an event driven logic simulation to check the function of a logic circuit, by using a logic simulator. The logic simulator includes at least one data base and a processing unit having a dummy element synthesizer. The dummy element is a tool for detecting changes in signals at a target cell or a target terminal. At the time that the logic simulation starts, the dummy element synthesizer produces the dummy element defining data, referring to or based on information stored in the data base, and combines the dummy element defining data and the logic circuit design data. Thus, for example, timing simulation at a target cell in the logic circuit or the check of the number of times of changes in signals at a target output terminal of the logic circuit, is executed during the event driven logic simulation.

Abstract: A method for cleaning an object involves the steps of treating an object by dipping the object in a cleaning liquid, rinsing the object with a rinse liquid having a first lower temperature for removing dust particles from the object, and rinsing the object subsequently using a rinse liquid having a second, higher temperature, for removing the cleaning liquid, wherein the first temperature is set such that no icing occurs on the dust particles.

Abstract: A PLL circuit of the pulse swallow-type prescaler system prevents erroneous module count operations such as are caused by a delay in the module signal, without the need to use a device which operates at high speeds or a device of large power. In a synthesizer of the pulse swallow-type prescaler system, a PLL circuit has a PLL COUNTER circuit and a module pulse generating circuit and a prescaler circuit has a prescaler counter, an extender circuit and a module control circuit which outputs a module control signal MO, for controlling the module operation, upon sensing the logic state of the module pulse generating signal MK, which is output by the module pulse signal generating circuit in response to the output signal MD of the PLL counter circuit.

Abstract: An electron-beam exposure system includes an astigmatic compensation circuit that increases a voltage applied across a pair of electrodes forming an electrostatic sub-deflector and simultaneously decreases a voltage applied across another pair of electrodes forming the same electrostatic sub-deflector with a same magnitude as in the case of increasing the voltage, wherein the magnitude of the voltage change is changed in response to the deflection of the electron-beam caused by a main deflector.

Abstract: A cleaning of a plasma chamber is done by a NF.sub.3 plasma treatment (typically under 1 to 1.5 Torr). The etching rate of an oxide layer can be improved by inserting, between the NF.sub.3 plasma treatments, a low pressure (lower than 10.sup.-1 Torr) plasma treatment preferably in a plasma of oxygen, water vapor, silane, fluorine, a hydrate compound, nitrogen trifluoride, or a mixture of nitrogen trifluoride with at least one of hydrogen fluoride, fluorine, water vapor and hydride compounds.

Abstract: A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

Abstract: This invention relates to a method and apparatus for reading out a synchronizing signal recorded in a data portion of each of a number of sectors stored in a recording medium such as an optical disc, a write-in-once type magneto-optical disc and so on. Even when detection of a synchronizing a signal has failed, the succeeding re-synchronizing signal can be detected reliably so that, although a first one divided unit portion of data is dropped out, data following the re-synchronizing signal can be read out positively, thus reducing data read error rate.

Abstract: A semiconductor memory device is disclosed for use in writing and reading data. The memory device is provided with a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to each of the word lines and bit lines, respectively. The memory device is provided with a precharger which precharges to set the potential of each bit line to a given level before the data on the memory cells can be read out onto the bit lines. The memory device is responsive to an address signal, and a controller for controlling the precharger. The controller activates the precharger so that all the bit lines are precharged when a previously selected word line changes following the change of the address signal.

Abstract: A constant voltage circuit adapted for connection between high voltage power source and low voltage power source terminals respectively to output a constant voltage signal from an output terminal in response to a control signal inputted to an input terminal. The circuit has a resistor circuit including a MOS transistor for connection to the high voltage power source and activated in response to the control signal. A current mirror section is connected between the resistor circuit and the low voltage power source terminal to generate an output voltage to be outputted from the output terminal. A feedback section is connected between the resistor circuit and the low voltage power source terminal to control the current mirror section to keep the output voltage constant by detecting deviation of the output voltage.

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: Disclosed is an apparatus for correcting error data contained in data read from an optical disk. The data correcting apparatus has a memory for storing data read out from the optical disk. The apparatus also has a syndrome generator for generating error syndrome data, and a circuit for detecting the position and value of data errors. The data correcting apparatus further includes a circuit for correcting errors in the read data stored in the memory, based on the error position and error value. The syndrome generator transfers a first ID data field for data identification together with the syndrome data via a first direct bus, provided between the syndrome generator and the detecting circuit. The detecting circuit transfers a second ID data field for data identification together with error information data via a second direct bus, provided between the detecting circuit and the data correcting circuit.

Abstract: An apparatus and method for transferring digital data is herein disclosed using a central processing unit and a direct memory access controller. Based on the control of the central processing unit, a direct memory access controller counts the number of words stored in a memory device by determining the number and position of the bytes contained in the words comprising the data to be transferred.

Abstract: An output buffer circuit includes a pull-down side transistor connected between an output terminal and a low-potential power source. The pull-down side transistor is driven by an input signal, such that when the pull-down side transistor is turned on by the input signal, a low level output signal is output from the output terminal. A pull-up circuit is connected between the output terminal and a high-potential power source, for changing the output signal to a high level in accordance with the input signal when the transistor is turned off in response to the input signal. The pull-up circuit ceases to function when the output signal goes high thereby creating a high impedance condition. The pull-up circuit includes an OR gate which receives the input signal and the output signal, and an inverter which receives an output signal of the OR gate. A differentiating circuit is provided, through which an output signal of the inverter circuit is output to the output terminal.

Abstract: An arithmetic logic unit (ALU) is disclosed, which is capable of shortening the zero-detection time. The ALU comprises a combinational circuit, a first and second zero detectors and a selector. The arithmetic device performs a mathematical operation on a first and second binary numbers to produce an operational result. The first zero detector determines whether the operational result of the arithmetic device is zero, based on the first and second binary numbers directly input to the first zero detector, concurrent with mathematical operation being executed by the combinational circuit. The second zero detector determines whether the operation result of the combinational circuit is zero, based on the operational result supplied thereto. The selector selects a detection output of one of the first and second zero detectors, based on a control signal supplied thereto.

Abstract: A method for ashing a resist on a wafer in a plasma reaction chamber comprises the steps of flowing a non-activated oxygen containing gas into the plasma reaction chamber immediately before loading the wafer to the plasma reaction chamber, and then carrying out a plasma ashing of the resist. In one of the preferred embodiments, after the reaction chamber was exposed to the atmosphere and then evacuated to vacuum, a mixed gas of oxygen (90% in volume) and water vapor (10% in volume) was flown into the reaction chamber with 1000 seem and 1 Torr for 5 min. and subsequently the ashing was carried out. The method prevents the ashing rate from decreasing with ashing time.